From 950cdbc3e25f021cb71693fb7c27b0588da1233d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 11 Dec 2020 17:00:42 +0100 Subject: soc/intel/skylake: Drop always-zero PowerLimit4 dt setting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unset devicetree settings default to zero, so the devicetree setting can be removed. Looks like no one needs it anyway. Change-Id: Iad94538c5465347b37a99c6c9f20988168661593 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/48575 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Furquan Shaikh --- src/soc/intel/skylake/chip.c | 2 +- src/soc/intel/skylake/chip.h | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 3eb72fa57a..c9519cdc29 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -303,7 +303,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; - tconfig->PowerLimit4 = config->PowerLimit4; + tconfig->PowerLimit4 = 0; /* * To disable HECI, the Psf needs to be left unlocked * by FSP till end of post sequence. Based on the devicetree diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 67739a4532..4d92410b65 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -87,9 +87,6 @@ struct soc_intel_skylake_config { /* TCC activation offset */ uint32_t tcc_offset; - /* Package PL4 power limit in Watts */ - u32 PowerLimit4; - /* Whether to ignore VT-d support of the SKU */ int ignore_vtd; -- cgit v1.2.3