From b4a45dcf9d442b311dec7396a55be917713a0d15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 26 Jul 2013 08:53:59 +0300 Subject: intel PCI ops: Remove explicit PCI MMCONF access MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17545 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/broadwell/pcie.c | 2 +- src/soc/intel/skylake/pcie.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 1c9b50cceb..355e17abfc 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -673,7 +673,7 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off) { /* Set max snoop and non-snoop latency for Broadwell */ - pci_mmio_write_config32(dev, off, 0x10031003); + pci_write_config32(dev, off, 0x10031003); } static struct pci_operations pcie_ops = { diff --git a/src/soc/intel/skylake/pcie.c b/src/soc/intel/skylake/pcie.c index 719abf33e3..d3eecff585 100644 --- a/src/soc/intel/skylake/pcie.c +++ b/src/soc/intel/skylake/pcie.c @@ -75,7 +75,7 @@ static void pch_pcie_init(struct device *dev) static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off) { /* Set max snoop and non-snoop latency for the SOC */ - pci_mmio_write_config32(dev, off, 0x10031003); + pci_write_config32(dev, off, 0x10031003); } static struct pci_operations pcie_ops = { -- cgit v1.2.3