From b50566ef63b560ed149db6aeb19004d7c0345275 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 4 Dec 2013 18:34:11 -0800 Subject: baytrail: Fix _CRS to build with new IASL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The new IASL is complaining about the PCI memory region not having consistent base/end/length values because they are placeholder that are fixed up in the method before returning. Put in some more valid placeholder values to make it happy. BUG=chromium:311294 BRANCH=none TEST=build and boot with IASL 20130117 on rambi Change-Id: I0e21adcce43deb14d3c2c45787ff8c9efc357c2f Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/178864 Reviewed-by: Aaron Durbin Commit-Queue: Duncan Laurie Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/4988 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/acpi/southcluster.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 1bc7eba650..49349c4649 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -160,8 +160,8 @@ Method (_CRS, 0, Serialized) // PCI Memory Region (Top of memory-0xfeafffff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0xfeafffff, 0x00000000, - 0xfeb00000,,, PMEM) + 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000, + 0x00100000,,, PMEM) // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, -- cgit v1.2.3