From e750b38e4834867ec362b59f150ef6ae9fe888c6 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 20 Jul 2018 23:31:59 +0200 Subject: cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures Software Developer’s Manual. The purpose is to differentiate with MSR_SMRR_PHYSx. Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/27584 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- src/soc/intel/apollolake/cpu.c | 4 ++-- src/soc/intel/baytrail/cpu.c | 4 ++-- src/soc/intel/braswell/cpu.c | 4 ++-- src/soc/intel/broadwell/smmrelocate.c | 4 ++-- src/soc/intel/cannonlake/smmrelocate.c | 4 ++-- src/soc/intel/denverton_ns/cpu.c | 4 ++-- src/soc/intel/fsp_baytrail/cpu.c | 4 ++-- src/soc/intel/fsp_broadwell_de/smmrelocate.c | 4 ++-- src/soc/intel/skylake/smmrelocate.c | 4 ++-- 9 files changed, 18 insertions(+), 18 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 690589443c..caa3bbf90f 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -223,10 +223,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, /* Set up SMRR. */ smrr.lo = relo_attrs.smrr_base; smrr.hi = 0; - wrmsr(SMRR_PHYS_BASE, smrr); + wrmsr(IA32_SMRR_PHYS_BASE, smrr); smrr.lo = relo_attrs.smrr_mask; smrr.hi = 0; - wrmsr(SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYS_MASK, smrr); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; } diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 77d2dda8bf..618430b9a8 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -179,10 +179,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, /* Set up SMRR. */ smrr.lo = relo_attrs.smrr_base; smrr.hi = 0; - wrmsr(SMRR_PHYS_BASE, smrr); + wrmsr(IA32_SMRR_PHYS_BASE, smrr); smrr.lo = relo_attrs.smrr_mask; smrr.hi = 0; - wrmsr(SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYS_MASK, smrr); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 31b1b78142..85b04ac81f 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -195,10 +195,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, /* Set up SMRR. */ smrr.lo = relo_attrs.smrr_base; smrr.hi = 0; - wrmsr(SMRR_PHYS_BASE, smrr); + wrmsr(IA32_SMRR_PHYS_BASE, smrr); smrr.lo = relo_attrs.smrr_mask; smrr.hi = 0; - wrmsr(SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYS_MASK, smrr); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 2d90ebce01..08b98e9de1 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -38,8 +38,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); } static inline void write_emrr(struct smm_relocation_params *relo_params) diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 3c60ef2b34..e688592a4c 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -41,8 +41,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); } static void update_save_state(int cpu, uintptr_t curr_smbase, diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index d486435a5b..b7b5550aaa 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -80,10 +80,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, /* Set up SMRR. */ smrr.lo = relo_attrs.smrr_base; smrr.hi = 0; - wrmsr(SMRR_PHYS_BASE, smrr); + wrmsr(IA32_SMRR_PHYS_BASE, smrr); smrr.lo = relo_attrs.smrr_mask; smrr.hi = 0; - wrmsr(SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYS_MASK, smrr); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; } diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index c7694b9824..a69d046e7b 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -139,10 +139,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, /* Set up SMRR. */ smrr.lo = relo_attrs.smrr_base; smrr.hi = 0; - wrmsr(SMRR_PHYS_BASE, smrr); + wrmsr(IA32_SMRR_PHYS_BASE, smrr); smrr.lo = relo_attrs.smrr_mask; smrr.hi = 0; - wrmsr(SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYS_MASK, smrr); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c index 28bc8c9710..fe7bc6f1ac 100644 --- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c +++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c @@ -39,8 +39,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); } static inline void write_prmrr(struct smm_relocation_params *relo_params) diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 6a8e64bd42..3db60f9e31 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -41,8 +41,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); } static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) -- cgit v1.2.3