From 131f3435fcd0e8beb94eb4d132788e5303a7550a Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Tue, 23 Jun 2020 10:19:17 +0800 Subject: soc/mediatek/mt8192: Do memory pll init before calibration Memory PLL is used to provide the basic clock for dram controller and DDRPHY. PLL must be initialized as predefined way. First, enable PLL POWER and ISO, wait at least 30us, release ISO, then configure PLL frequency and enable PLL master switch. At last, enable control ability for SPM to switch between active and idle when system is switched between normal and low power mode. TEST=Confirm Memory PLL frequency is right by frequency meter Signed-off-by: Huayang Duan Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44702 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin Reviewed-by: Frans Hendriks --- src/soc/mediatek/common/include/soc/pll_common.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/soc/mediatek/common') diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index d9ba2308e9..ae6ad64ded 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -3,6 +3,7 @@ #ifndef SOC_MEDIATEK_PLL_COMMON_H #define SOC_MEDIATEK_PLL_COMMON_H +#include #include #include @@ -54,6 +55,15 @@ struct pll { .div_rate = _div_rate, \ } +/* every PLL can share the same POWER_EN/ISO_EN/EN bits, use the common BITFIELD macro */ +DEFINE_BIT(PLL_ENABLE, 0) + +DEFINE_BIT(PLL_POWER_ENABLE, 0) +DEFINE_BIT(PLL_ISO_ENABLE, 1) +DEFINE_BITFIELD(PLL_POWER_ISO_ENABLE, 1, 0) + +DEFINE_BITFIELD(PLL_CON1, 31, 0) + void pll_set_pcw_change(const struct pll *pll); void mux_set_sel(const struct mux *mux, u32 sel); int pll_set_rate(const struct pll *pll, u32 rate); -- cgit v1.2.3