From 55009af42c39f413c49503670ce9bc2858974962 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Dec 2019 22:03:27 -0800 Subject: Change all clrsetbits_leXX() to clrsetbitsXX() This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/mediatek/mt8173/pmic_wrap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/mediatek/mt8173/pmic_wrap.c') diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c index af88343c14..a15447c20f 100644 --- a/src/soc/mediatek/mt8173/pmic_wrap.c +++ b/src/soc/mediatek/mt8173/pmic_wrap.c @@ -170,11 +170,11 @@ s32 pwrap_init(void) s32 sub_return1 = 0; u16 rdata = 0x0; - setbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); + setbits32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); /* add 1us delay for toggling SW reset */ udelay(1); /* clear reset bit */ - clrbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); + clrbits32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); /* Enable DCM */ write32(&mtk_pwrap->dcm_en, 3); -- cgit v1.2.3