From 47d46d0a18af3ec140c07b8e3a88dd3fb53c331e Mon Sep 17 00:00:00 2001 From: Ran Bi Date: Fri, 26 Oct 2018 15:18:09 +0800 Subject: mediatek/mt8183: Add RTC support This patch implements RTC initialization. 1. initialization dcxo 2. rtc clock using dcxo 32k 3. export RTC_32K1V8_0 to SOC, export RTC_32K1V8_1 to WLAN 4. rtc register initialization 5. refactor the driver common part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Icccb9360a507fcbfd865b107cd3630e71c810d55 Signed-off-by: Ran Bi Reviewed-on: https://review.coreboot.org/c/31046 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/mediatek/mt8173/Makefile.inc | 4 +- src/soc/mediatek/mt8173/include/soc/rtc.h | 74 +---------- src/soc/mediatek/mt8173/rtc.c | 197 ++---------------------------- 3 files changed, 19 insertions(+), 256 deletions(-) (limited to 'src/soc/mediatek/mt8173') diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 4ccc218e4d..0ffa1965a9 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -60,7 +60,7 @@ romstage-y += memory.c romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c romstage-y += ../common/mmu_operations.c mmu_operations.c -romstage-y += rtc.c +romstage-y += ../common/rtc.c rtc.c ################################################################################ @@ -77,7 +77,7 @@ ramstage-y += da9212.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/wdt.c ../common/reset.c ramstage-y += ../common/pll.c pll.c -ramstage-y += rtc.c +ramstage-y += ../common/rtc.c rtc.c ramstage-y += ../common/usb.c usb.c diff --git a/src/soc/mediatek/mt8173/include/soc/rtc.h b/src/soc/mediatek/mt8173/include/soc/rtc.h index dd3546a13c..fe5cbac277 100644 --- a/src/soc/mediatek/mt8173/include/soc/rtc.h +++ b/src/soc/mediatek/mt8173/include/soc/rtc.h @@ -16,28 +16,10 @@ #ifndef SOC_MEDIATEK_MT8173_RTC_H #define SOC_MEDIATEK_MT8173_RTC_H +#include #include #include "mt6391.h" -/* - * Default values for RTC initialization - * Year (YEA) : 1970 ~ 2037 - * Month (MTH) : 1 ~ 12 - * Day of Month (DOM): 1 ~ 31 - */ - -enum { - RTC_DEFAULT_YEA = 2010, - RTC_DEFAULT_MTH = 1, - RTC_DEFAULT_DOM = 1, - RTC_DEFAULT_DOW = 5 -}; - -enum { - RTC_2SEC_REBOOT_ENABLE = 1, - RTC_2SEC_MODE = 2 -}; - /* RTC registers */ enum { RTC_BBPU = 0xE000, @@ -88,16 +70,6 @@ enum { RTC_CALI = 0xE03A }; -enum { - RTC_OSC32CON_UNLOCK1 = 0x1A57, - RTC_OSC32CON_UNLOCK2 = 0x2B68 -}; - -enum { - RTC_PROT_UNLOCK1 = 0x586A, - RTC_PROT_UNLOCK2 = 0x9136 -}; - enum { RTC_BBPU_PWREN = 1U << 0, RTC_BBPU_BBPU = 1U << 2, @@ -109,34 +81,11 @@ enum { RTC_CBUSY_TIMEOUT_US = 800 }; -enum { - RTC_BBPU_KEY = 0x43 << 8 -}; - -enum { - RTC_IRQ_STA_AL = 1U << 0, - RTC_IRQ_STA_TC = 1U << 1, - RTC_IRQ_STA_LP = 1U << 3 -}; - -enum { - RTC_IRQ_EN_AL = 1U << 0, - RTC_IRQ_EN_TC = 1U << 1, - RTC_IRQ_EN_ONESHOT = 1U << 2, - RTC_IRQ_EN_LP = 1U << 3, - RTC_IRQ_EN_ONESHOT_AL = RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL -}; - enum { RTC_OSC32CON_AMPEN = 1U << 8, RTC_OSC32CON_LNBUFEN = 1U << 11 }; -enum { - RTC_POWERKEY1_KEY = 0xa357, - RTC_POWERKEY2_KEY = 0x67d2 -}; - enum { RTC_CON_LPEN = 1U << 2, RTC_CON_LPRST = 1U << 3, @@ -161,24 +110,9 @@ enum { RTC_CALI_BBPU_2SEC_STAT = 1U << 11 }; -enum { - RTC_SPAR0_32K_LESS = 1U << 6 -}; - -enum { - RTC_MIN_YEAR = 1968, - RTC_BASE_YEAR = 1900, - RTC_MIN_YEAR_OFFSET = RTC_MIN_YEAR - RTC_BASE_YEAR, - - RTC_NUM_YEARS = 128 -}; - -enum { - RTC_STATE_REBOOT = 0, - RTC_STATE_RECOVER = 1, - RTC_STATE_INIT = 2 -}; - +/* external API */ +void rtc_osc_init(void); +int rtc_init(u8 recover); void rtc_boot(void); #endif /* SOC_MEDIATEK_MT8173_RTC_H */ diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index 153e9b4249..5b7d486d87 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -13,133 +13,13 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include -#include -#include - +#include +#include #include #include -#include #define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) -/* ensure rtc write success */ -static inline int rtc_busy_wait(void) -{ - struct stopwatch sw; - u16 bbpu; - - stopwatch_init_usecs_expire(&sw, RTC_CBUSY_TIMEOUT_US); - - do { - pwrap_read(RTC_BBPU, &bbpu); - /* Time > 1sec, time out and set recovery mode enable.*/ - if (stopwatch_expired(&sw)) { - printk(BIOS_INFO, "[RTC] BBPU CBUSY time out !!\n"); - return 0; - } - } while (bbpu & RTC_BBPU_CBUSY); - - return 1; -} - -static int write_trigger(void) -{ - pwrap_write(RTC_WRTGR, 1); - return rtc_busy_wait(); -} - -/* unlock rtc write interface */ -static int writeif_unlock(void) -{ - pwrap_write(RTC_PROT, RTC_PROT_UNLOCK1); - if (!write_trigger()) - return 0; - pwrap_write(RTC_PROT, RTC_PROT_UNLOCK2); - if (!write_trigger()) - return 0; - - return 1; -} - -/* set rtc time */ -int rtc_set(const struct rtc_time *time) -{ - return -1; -} - -/* get rtc time */ -int rtc_get(struct rtc_time *time) -{ - u16 value; - - pwrap_read(RTC_TC_SEC, &value); - time->sec = value; - pwrap_read(RTC_TC_MIN, &value); - time->min = value; - pwrap_read(RTC_TC_HOU, &value); - time->hour = value; - pwrap_read(RTC_TC_DOM, &value); - time->mday = value; - pwrap_read(RTC_TC_MTH, &value); - time->mon = value; - pwrap_read(RTC_TC_YEA, &value); - time->year = (value + RTC_MIN_YEAR_OFFSET) % 100; - - return 0; -} - -/* set rtc xosc setting */ -static void rtc_xosc_write(u16 val) -{ - pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1); - udelay(200); - pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2); - udelay(200); - - pwrap_write(RTC_OSC32CON, val); - udelay(200); - pwrap_write_field(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0, 0); - write_trigger(); -} - -/* initialize rtc related registers */ -static int rtc_reg_init(void) -{ - u16 irqsta; - - pwrap_write(RTC_IRQ_EN, 0); - pwrap_write(RTC_CII_EN, 0); - pwrap_write(RTC_AL_MASK, 0); - pwrap_write(RTC_AL_YEA, 1970 - RTC_MIN_YEAR); - pwrap_write(RTC_AL_MTH, 1); - pwrap_write(RTC_AL_DOM, 1); - pwrap_write(RTC_AL_DOW, 4); - pwrap_write(RTC_AL_HOU, 0); - pwrap_write(RTC_AL_MIN, 0); - pwrap_write(RTC_AL_SEC, 0); - - pwrap_write(RTC_DIFF, 0); - pwrap_write(RTC_CALI, 0); - if (!write_trigger()) - return 0; - - pwrap_read(RTC_IRQ_STA, &irqsta); /* read clear */ - - /* init time counters after resetting RTC_DIFF and RTC_CALI */ - pwrap_write(RTC_TC_YEA, RTC_DEFAULT_YEA - RTC_MIN_YEAR); - pwrap_write(RTC_TC_MTH, RTC_DEFAULT_MTH); - pwrap_write(RTC_TC_DOM, RTC_DEFAULT_DOM); - pwrap_write(RTC_TC_DOW, RTC_DEFAULT_DOW); - pwrap_write(RTC_TC_HOU, 0); - pwrap_write(RTC_TC_MIN, 0); - pwrap_write(RTC_TC_SEC, 0); - - return write_trigger(); -} /* initialize rtc related gpio */ static int rtc_gpio_init(void) @@ -155,11 +35,11 @@ static int rtc_gpio_init(void) con |= (RTC_CON_GPEN | RTC_CON_GOE); con &= ~(RTC_CON_F32KOB); pwrap_write(RTC_CON, con); - return write_trigger(); + return rtc_write_trigger(); } /* set xosc mode */ -static void rtc_osc_init(void) +void rtc_osc_init(void) { u16 con; @@ -176,26 +56,26 @@ static void rtc_osc_init(void) static int rtc_lpd_init(void) { pwrap_write_field(RTC_CON, RTC_CON_LPEN, RTC_CON_LPRST, 0); - if (!write_trigger()) + if (!rtc_write_trigger()) return 0; pwrap_write_field(RTC_CON, RTC_CON_LPRST, 0, 0); - if (!write_trigger()) + if (!rtc_write_trigger()) return 0; pwrap_write_field(RTC_CON, 0, RTC_CON_LPRST, 0); - if (!write_trigger()) + if (!rtc_write_trigger()) return 0; return 1; } /* rtc init check */ -static int rtc_init(u8 recover) +int rtc_init(u8 recover) { printk(BIOS_INFO, "[RTC] %s recovery: %d\n", __func__, recover); - if (!writeif_unlock()) + if (!rtc_writeif_unlock()) return 0; if (!rtc_gpio_init()) @@ -213,7 +93,7 @@ static int rtc_init(u8 recover) /* write powerkeys */ pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); - if (!write_trigger()) + if (!rtc_write_trigger()) return 0; if (recover) @@ -238,8 +118,8 @@ static void rtc_bbpu_power_on(void) /* pull PWRBB high */ bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_BBPU | RTC_BBPU_PWREN; pwrap_write(RTC_BBPU, bbpu); - ret = write_trigger(); - printk(BIOS_INFO, "[RTC] %s write_trigger=%d\n", __func__, ret); + ret = rtc_write_trigger(); + printk(BIOS_INFO, "[RTC] %s rtc_write_trigger=%d\n", __func__, ret); /* enable DCXO to transform external 32KHz clock to 26MHz clock directly sent to SoC */ @@ -256,63 +136,12 @@ static void rtc_bbpu_power_on(void) pwrap_write_field(PMIC_RG_TOP_CKPDN2, 0x1, 0, 14); } -static u8 rtc_check_state(void) -{ - u16 con; - u16 pwrky1; - u16 pwrky2; - - pwrap_read(RTC_CON, &con); - pwrap_read(RTC_POWERKEY1, &pwrky1); - pwrap_read(RTC_POWERKEY2, &pwrky2); - - if (con & RTC_CON_LPSTA_RAW) - return RTC_STATE_INIT; - - if (!rtc_busy_wait()) - return RTC_STATE_RECOVER; - - if (!writeif_unlock()) - return RTC_STATE_RECOVER; - - if (pwrky1 != RTC_POWERKEY1_KEY || pwrky2 != RTC_POWERKEY2_KEY) - return RTC_STATE_INIT; - else - return RTC_STATE_REBOOT; -} - /* the rtc boot flow entry */ void rtc_boot(void) { - u16 bbpu; - u16 con; - u16 irqsta; - pwrap_write(PMIC_RG_TOP_CKPDN, 0); pwrap_write(PMIC_RG_TOP_CKPDN2, 0); - switch (rtc_check_state()) { - case RTC_STATE_REBOOT: - pwrap_write_field(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0, - 0); - write_trigger(); - rtc_osc_init(); - break; - case RTC_STATE_RECOVER: - rtc_init(1); - break; - case RTC_STATE_INIT: - default: - if (!rtc_init(0)) - rtc_init(1); - break; - } - - pwrap_read(RTC_IRQ_STA, &irqsta); /* Read clear */ - pwrap_read(RTC_BBPU, &bbpu); - pwrap_read(RTC_CON, &con); - - printk(BIOS_INFO, "[RTC] irqsta = %x", irqsta); - printk(BIOS_INFO, " bbpu = %#x, con = %#x\n", bbpu, con); + rtc_boot_common(); rtc_bbpu_power_on(); } -- cgit v1.2.3