From e621d8f11a2bdad4920cbb7c4293fdfd98adf4bd Mon Sep 17 00:00:00 2001 From: Weiyi Lu Date: Tue, 19 Mar 2019 13:39:12 +0800 Subject: mediatek/mt8183: Add infra group DCM setting Add infra group DCM (Dynamic Clock Management) settings, which slows down OR gate clocks while hardware is in idle state. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I4741dfb7b984deb92171f370e5fb2593829d74c2 Signed-off-by: Weiyi Lu Reviewed-on: https://review.coreboot.org/c/coreboot/+/31977 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: You-Cheng Syu --- src/soc/mediatek/mt8183/include/soc/pll.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/soc/mediatek/mt8183/include') diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h index 2a72e2c61c..3807e0087e 100644 --- a/src/soc/mediatek/mt8183/include/soc/pll.h +++ b/src/soc/mediatek/mt8183/include/soc/pll.h @@ -270,4 +270,13 @@ enum { SPI_HZ = MAINPLL_D5_D2_HZ, }; +enum { + DCM_INFRA_BUS_MASK = 0x40907ffb, + DCM_INFRA_BUS_ON = 0x40904203, + DCM_INFRA_MEM_ON = 0x1 << 27, + DCM_INFRA_P2PRX_MASK = 0xf, + DCM_INFRA_PERI_MASK = 0xf03ffffb, + DCM_INFRA_PERI_ON = 0xf03f83e3, +}; + #endif /* SOC_MEDIATEK_MT8183_PLL_H */ -- cgit v1.2.3