From 47095d5ec35b4cbff9d4660cfe9521ed17a0d1ed Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Tue, 27 Apr 2021 21:20:06 +0800 Subject: soc/mediatek: Move the common part of SPI drivers to common/ The SPI drivers can be shared by MT8183, MT8192 and MT8195. TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Cherry P0 Signed-off-by: Rex-BC Chen Change-Id: I7bb7809a88fbda67eca67ecfde45b9cb5f09dffe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52854 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8183/include/soc/spi.h | 47 +++++++++---------------------- src/soc/mediatek/mt8183/spi.c | 17 ----------- 2 files changed, 13 insertions(+), 51 deletions(-) (limited to 'src/soc/mediatek/mt8183') diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h index 5efa618d39..5bc70e5d36 100644 --- a/src/soc/mediatek/mt8183/include/soc/spi.h +++ b/src/soc/mediatek/mt8183/include/soc/spi.h @@ -7,39 +7,18 @@ #define SPI_BUS_NUMBER 6 -/* SPI peripheral register map. */ -typedef struct mtk_spi_regs { - uint32_t spi_cfg0_reg; - uint32_t spi_cfg1_reg; - uint32_t spi_tx_src_reg; - uint32_t spi_rx_dst_reg; - uint32_t spi_tx_data_reg; - uint32_t spi_rx_data_reg; - uint32_t spi_cmd_reg; - uint32_t spi_status0_reg; - uint32_t spi_status1_reg; - uint32_t spi_pad_macro_sel_reg; - uint32_t spi_cfg2_reg; - uint32_t spi_tx_src_64_reg; - uint32_t spi_rx_dst_64_reg; -} mtk_spi_regs; - -check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); - -enum { - SPI_CFG0_CS_HOLD_SHIFT = 0, - SPI_CFG0_CS_SETUP_SHIFT = 16, -}; - -enum { - SPI_CFG2_SCK_LOW_SHIFT = 0, - SPI_CFG2_SCK_HIGH_SHIFT = 16, -}; - -enum { - SPI_CFG1_TICK_DLY_SHIFT = 29, - SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT, - -}; +#define GET_SCK_REG(x) x->spi_cfg2_reg + +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) + +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) + +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) +DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) + #endif diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index 87362dc33c..c172f377da 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -103,23 +103,6 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select) gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); } -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, - unsigned int tick_dly) -{ - write32(®s->spi_cfg0_reg, - ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | - ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - - write32(®s->spi_cfg2_reg, - ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | - ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT)); - - clrsetbits32(®s->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | - SPI_CFG1_CS_IDLE_MASK, - (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | - ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); -} - const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &spi_ctrlr, -- cgit v1.2.3