From ba616438e9e81355eb447034fc3159c6db80a69b Mon Sep 17 00:00:00 2001
From: CK Hu <ck.hu@mediatek.com>
Date: Mon, 11 May 2020 16:27:53 +0800
Subject: soc/mediatek/mt8192: Use SPI-NOR as flash controller

Add a SPI-NOR flash controller which supports pio mode.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I1e38672a532dd8234b3ef24c84113888c8795810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
---
 src/soc/mediatek/mt8192/spi.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'src/soc/mediatek/mt8192/spi.c')

diff --git a/src/soc/mediatek/mt8192/spi.c b/src/soc/mediatek/mt8192/spi.c
index 577536a9f7..d35e5ad3ca 100644
--- a/src/soc/mediatek/mt8192/spi.c
+++ b/src/soc/mediatek/mt8192/spi.c
@@ -3,6 +3,7 @@
 #include <device/mmio.h>
 #include <assert.h>
 #include <soc/addressmap.h>
+#include <soc/flash_controller.h>
 #include <soc/gpio.h>
 #include <soc/spi.h>
 
@@ -128,12 +129,22 @@ void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks,
 		     ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
 }
 
+static const struct spi_ctrlr spi_flash_ctrlr = {
+	.max_xfer_size = 65535,
+	.flash_probe = mtk_spi_flash_probe,
+};
+
 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
 	{
 		.ctrlr = &spi_ctrlr,
 		.bus_start = 0,
 		.bus_end = SPI_BUS_NUMBER - 1,
 	},
+	{
+		.ctrlr = &spi_flash_ctrlr,
+		.bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
+		.bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
+	},
 };
 
 const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
-- 
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