From d21a329866a1299b180f8b14b6c73bee3d754e57 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Thu, 19 Feb 2015 14:08:04 -0800 Subject: arm(64): Replace write32() and friends with writel() This patch is a raw application of the following spatch to the directories src/arch/arm(64)?, src/mainboard/, src/soc/ and src/drivers/gic: @@ expression A, V; @@ - write32(V, A) + writel(V, A) @@ expression A, V; @@ - write16(V, A) + writew(V, A) @@ expression A, V; @@ - write8(V, A) + writeb(V, A) This replaces all uses of write{32,16,8}() with write{l,w,b}() which is currently equivalent and much more common. This is a preparatory step that will allow us to easier flip them all at once to the new write32(a,v) model. BRANCH=none BUG=chromium:451388 TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky. Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09 Signed-off-by: Patrick Georgi Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24 Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d Original-Signed-off-by: Julius Werner Original-Reviewed-on: https://chromium-review.googlesource.com/254862 Reviewed-on: http://review.coreboot.org/9834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/nvidia/tegra/usb.c | 68 ++++++++++++---------------------------------- 1 file changed, 17 insertions(+), 51 deletions(-) (limited to 'src/soc/nvidia/tegra/usb.c') diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c index 3268ee1a74..c666c40f3b 100644 --- a/src/soc/nvidia/tegra/usb.c +++ b/src/soc/nvidia/tegra/usb.c @@ -126,7 +126,7 @@ static void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type t { int timeout = 1000; - write32(1 << 1, &usb->ehci_usbcmd); /* Host Controller Reset */ + writel(1 << 1, &usb->ehci_usbcmd); /* Host Controller Reset */ /* TODO: Resets are long, find way to parallelize... or just use XHCI */ while (--timeout && (read32(&usb->ehci_usbcmd) & 1 << 1)) /* wait for HC to reset */; @@ -137,11 +137,11 @@ static void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type t } /* Controller mode: HOST */ - write32(3 << 0, &usb->usb_mode); + writel(3 << 0, &usb->usb_mode); /* Parallel transceiver selct */ - write32(type << 29, &usb->lpm_ctrl); + writel(type << 29, &usb->lpm_ctrl); /* Tx FIFO Burst thresh */ - write32(0x10 << 16, &usb->tx_fill_tuning); + writel(0x10 << 16, &usb->tx_fill_tuning); } /* Assume USBx clocked, out of reset, UTMI+ PLL set up, SAMP_x out of pwrdn */ @@ -157,61 +157,27 @@ void usb_setup_utmip(void *usb_base) udelay(1); /* Take stuff out of pwrdn and add some magic numbers from U-Boot */ - write32(0x8 << 25 | /* HS slew rate [10:4] */ - 0x3 << 22 | /* HS driver output 'SETUP' [6:4] */ - 0 << 21 | /* LS bias selection */ - 0 << 18 | /* PDZI pwrdn */ - 0 << 16 | /* PD2 pwrdn */ - 0 << 14 | /* PD pwrdn */ - 1 << 13 | /* (rst) HS receiver terminations */ - 0x1 << 10 | /* (rst) LS falling slew rate */ - 0x1 << 8 | /* (rst) LS rising slew rate */ - 0x4 << 0 | /* HS driver output 'SETUP' [3:0] */ - 0, &usb->utmip.xcvr0); - write32(0x7 << 18 | /* Termination range adjustment */ - 0 << 4 | /* PDDR pwrdn */ - 0 << 2 | /* PDCHRP pwrdn */ - 0 << 0 | /* PDDISC pwrdn */ - 0, &usb->utmip.xcvr1); - write32(1 << 19 | /* FS send initial J before sync(?) */ - 1 << 16 | /* (rst) Allow stuff error on SoP */ - 1 << 9 | /* (rst) Check disc only on EoP */ - 0, &usb->utmip.tx); - write32(0x2 << 30 | /* (rst) Keep pattern on active */ - 1 << 28 | /* (rst) Realign inertia on pkt */ - 0x1 << 24 | /* (rst) edges-1 to move sampling */ - 0x3 << 21 | /* (rst) squelch delay on EoP */ - 0x11 << 15 | /* cycles until IDLE */ - 0x10 << 10 | /* elastic input depth */ - 0, &usb->utmip.hsrx0); + writel(0x8 << 25 | 0x3 << 22 | 0 << 21 | 0 << 18 | 0 << 16 | 0 << 14 | 1 << 13 | 0x1 << 10 | 0x1 << 8 | 0x4 << 0 | 0, + &usb->utmip.xcvr0); + writel(0x7 << 18 | 0 << 4 | 0 << 2 | 0 << 0 | 0, &usb->utmip.xcvr1); + writel(1 << 19 | 1 << 16 | 1 << 9 | 0, &usb->utmip.tx); + writel(0x2 << 30 | 1 << 28 | 0x1 << 24 | 0x3 << 21 | 0x11 << 15 | 0x10 << 10 | 0, + &usb->utmip.hsrx0); /* U-Boot claims the USBD values for these are used across all UTMI+ * PHYs. That sounds so horribly wrong that I'm not going to implement * it, but keep it in mind if we're ever not using the USBD port. */ - write32(0x1 << 24 | /* HS disconnect detect level [2] */ - 1 << 23 | /* (rst) IDPD value */ - 1 << 22 | /* (rst) IDPD select */ - 1 << 11 | /* (rst) OTG pwrdn */ - 0 << 10 | /* bias pwrdn */ - 0x1 << 2 | /* HS disconnect detect level [1:0] */ - 0x2 << 0 | /* HS squelch detect level */ - 0, &usb->utmip.bias0); - - write32(khz / 2200 << 3 | /* bias pwrdn cycles (20us?) */ - 1 << 2 | /* (rst) VBUS wakeup pwrdn */ - 0 << 0 | /* PDTRK pwrdn */ - 0, &usb->utmip.bias1); - - write32(0xffff << 16 | /* (rst) */ - 25 * khz / 10 << 0 | /* TODO: what's this, really? */ - 0, &usb->utmip.debounce); + writel(0x1 << 24 | 1 << 23 | 1 << 22 | 1 << 11 | 0 << 10 | 0x1 << 2 | 0x2 << 0 | 0, + &usb->utmip.bias0); + + writel(khz / 2200 << 3 | 1 << 2 | 0 << 0 | 0, &usb->utmip.bias1); + + writel(0xffff << 16 | 25 * khz / 10 << 0 | 0, &usb->utmip.debounce); udelay(1); setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ - write32(1 << 12 | /* UTMI+ enable */ - 0 << 11 | /* UTMI+ reset */ - 0, &usb->suspend_ctrl); + writel(1 << 12 | 0 << 11 | 0, &usb->suspend_ctrl); usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP); printk(BIOS_DEBUG, "USB controller @ %p set up with UTMI+ PHY\n",usb_base); -- cgit v1.2.3