From 4058d7b9d465ce730a7043e0ce2ae780a7627d81 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 22 Aug 2014 10:24:27 -0500 Subject: tegra132: refactor cpu startup code In order to more easily bring up the 2nd core refactor the cpu startup logic. A common 32bit_entry.S is compiled both for romstage and ramstage to provide the common 32-bit entry point. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted ryu to the kernel. Also, can get the 2nd core up out of reset. Change-Id: I0c2c9f637189009767e8d5510732678c64e62a2a Signed-off-by: Patrick Georgi Original-Commit-Id: 7394b271bf67dfad8a601f41faaac8f07ae6d4a5 Original-Change-Id: Id810df95c53d3dc8b36d8bd21851d3b0006a8bc2 Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/213850 Original-Reviewed-by: Furquan Shaikh Reviewed-on: http://review.coreboot.org/9001 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/nvidia/tegra132/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/nvidia/tegra132/Makefile.inc') diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index b489d52afb..96961c8027 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -20,6 +20,7 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif +romstage-y += 32bit_reset.S romstage-y += romstage_asm.S romstage-y += addressmap.c romstage-y += cbfs.c @@ -27,6 +28,7 @@ romstage-y += cbmem.c romstage-y += timer.c romstage-y += ccplex.c romstage-y += clock.c +romstage-y += cpu.c romstage-y += reset.c romstage-y += spi.c romstage-y += i2c.c @@ -45,9 +47,11 @@ romstage-y += ../tegra/pinmux.c romstage-y += ../tegra/usb.c romstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-y += 32bit_reset.S ramstage-y += addressmap.c ramstage-y += cbfs.c ramstage-y += cbmem.c +ramstage-y += cpu.c ramstage-y += timer.c ramstage-y += clock.c ramstage-y += soc.c -- cgit v1.2.3