From cad9e7a6ecf2db58ba30c49847851248d4712110 Mon Sep 17 00:00:00 2001 From: Yen Lin Date: Wed, 6 May 2015 13:56:50 -0700 Subject: t210: set CAR2PMC_CPU_ACK_WIDTH to 0 HW team has suggested to set CAR2PMC_CPU_ACK_WIDTH to 0. BUG=None BRANCH=None TEST=Tested on Smaug; still boot to kernel Change-Id: I4d13a4048b73455b16da7a40c408c912fa97e4e7 Signed-off-by: Patrick Georgi Original-Commit-Id: 8891a79e72af26d986af9e415149d4ca0aa6fedd Original-Change-Id: I850a6756d7743993802fb85aad403e4cbef7a661 Original-Signed-off-by: Yen Lin Original-Reviewed-on: https://chromium-review.googlesource.com/282416 Original-Reviewed-by: Furquan Shaikh Reviewed-on: http://review.coreboot.org/10841 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/nvidia/tegra210/include/soc/clk_rst.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/nvidia/tegra210/include') diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h index 817a041422..87790d5fb1 100644 --- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h @@ -534,6 +534,9 @@ enum { #define PCLK_DIVISOR_SHIFT 0 #define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) +/* CPU_SOFTRST_CTRL2_0 0x388 */ +#define CAR2PMC_CPU_ACK_WIDTH_MASK 0xfff + /* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ #define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) -- cgit v1.2.3