From 21ee13c3ca5581c41a53a7e255709aa3c22b373a Mon Sep 17 00:00:00 2001 From: Yen Lin Date: Thu, 16 Jul 2015 10:23:34 -0700 Subject: t210: lp0_resume: set CAR2PMC_CPU_ACK_WIDTH to 0 Like in cold boot path, need to set CAR2PMC_CPU_ACK_WIDTH to 0 in lp0 resume path. BUG=chrome-os-partner:40741 BRANCH=None TEST=Tested on Smaug; able to suspend/resume Change-Id: Iffd7fa4d0266e2ec482ec17e5203ceff8afe748f Signed-off-by: Patrick Georgi Original-Commit-Id: 052b649b1e6a4e34d621d710ee43aec7149ab8a8 Original-Change-Id: Icdf9879469485fb37b820b30c9663eda528ac013 Original-Signed-off-by: Yen Lin Original-Reviewed-on: https://chromium-review.googlesource.com/286600 Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Tom Warren Reviewed-on: http://review.coreboot.org/11037 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/soc/nvidia/tegra210/lp0') diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 168c95a5d9..dc61cbac67 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -146,6 +146,13 @@ enum { CLK_ENB_CSITE = 0x1 << 9 }; +static uint32_t *clk_rst_cpu_softrst_ctrl2_ptr = + (void *)(CLK_RST_BASE + 0x388); +enum { + CAR2PMC_CPU_ACK_WIDTH_SHIFT = 0, + CAR2PMC_CPU_ACK_WIDTH_MASK = 0xfff << CAR2PMC_CPU_ACK_WIDTH_SHIFT +}; + static uint32_t *clk_rst_clk_enb_v_set_ptr = (void *)(CLK_RST_BASE + 0x440); enum { CLK_ENB_CPUG = 0x1 << 0, @@ -787,6 +794,9 @@ void lp0_resume(void) /* Disable PLLX since it isn't used in the kernel as CPU clk source. */ clrbits32(PLLX_ENABLE, clk_rst_pllx_base_ptr); + /* Set CAR2PMC_CPU_ACK_WIDTH to 0 */ + clrbits32(CAR2PMC_CPU_ACK_WIDTH_MASK, clk_rst_cpu_softrst_ctrl2_ptr); + /* Clear PMC_SCRATCH190 */ clrbits32(1, pmc_scratch190_ptr); -- cgit v1.2.3