From 40a3e321d4e8f2877de1700db67b8c7f7ea89820 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 22 Jun 2015 19:41:29 +0200 Subject: nvidia/tegra210: add new SoC This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I81853434600390d643160fe57554495b2bfe60ab Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/10633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/nvidia/tegra210/ram_code.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 src/soc/nvidia/tegra210/ram_code.c (limited to 'src/soc/nvidia/tegra210/ram_code.c') diff --git a/src/soc/nvidia/tegra210/ram_code.c b/src/soc/nvidia/tegra210/ram_code.c new file mode 100644 index 0000000000..8715410e76 --- /dev/null +++ b/src/soc/nvidia/tegra210/ram_code.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +uint32_t sdram_get_ram_code(void) +{ + struct apbmisc *misc = (struct apbmisc *)TEGRA_APB_MISC_BASE; + + return (read32(&misc->pp_strapping_opt_a) & + PP_STRAPPING_OPT_A_RAM_CODE_MASK) >> + PP_STRAPPING_OPT_A_RAM_CODE_SHIFT; +} -- cgit v1.2.3