From 6a00113de8b9060a7227bcfa79b3786e3e592a33 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Thu, 13 Jul 2017 02:20:27 +0200 Subject: Rename __attribute__((packed)) --> __packed Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/nvidia/tegra124/include/soc/clk_rst.h | 4 +++- src/soc/nvidia/tegra124/include/soc/dma.h | 5 +++-- src/soc/nvidia/tegra124/include/soc/emc.h | 3 ++- src/soc/nvidia/tegra124/include/soc/spi.h | 3 ++- src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 3 ++- src/soc/nvidia/tegra124/uart.c | 3 ++- src/soc/nvidia/tegra210/include/soc/clk_rst.h | 3 ++- src/soc/nvidia/tegra210/include/soc/clst_clk.h | 4 +++- src/soc/nvidia/tegra210/include/soc/dma.h | 5 +++-- src/soc/nvidia/tegra210/include/soc/emc.h | 3 ++- src/soc/nvidia/tegra210/include/soc/spi.h | 3 ++- src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 3 ++- src/soc/nvidia/tegra210/uart.c | 3 ++- 13 files changed, 30 insertions(+), 15 deletions(-) (limited to 'src/soc/nvidia') diff --git a/src/soc/nvidia/tegra124/include/soc/clk_rst.h b/src/soc/nvidia/tegra124/include/soc/clk_rst.h index f7d78eee17..165b823145 100644 --- a/src/soc/nvidia/tegra124/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra124/include/soc/clk_rst.h @@ -14,8 +14,10 @@ #ifndef _TEGRA124_CLK_RST_H_ #define _TEGRA124_CLK_RST_H_ +#include + /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ -struct __attribute__ ((__packed__)) clk_rst_ctlr { +struct __packed clk_rst_ctlr { u32 rst_src; /* _RST_SOURCE, 0x000 */ u32 rst_dev_l; /* _RST_DEVICES_L, 0x004 */ u32 rst_dev_h; /* _RST_DEVICES_H, 0x008 */ diff --git a/src/soc/nvidia/tegra124/include/soc/dma.h b/src/soc/nvidia/tegra124/include/soc/dma.h index 53edc92369..4d3e9f6608 100644 --- a/src/soc/nvidia/tegra124/include/soc/dma.h +++ b/src/soc/nvidia/tegra124/include/soc/dma.h @@ -17,6 +17,7 @@ #define __NVIDIA_TEGRA124_DMA_H__ #include +#include #include /* @@ -66,7 +67,7 @@ struct apb_dma { u32 chan_wt_reg2; /* 0x4c */ u32 chan_wr_reg3; /* 0x50 */ u32 channel_swid1; /* 0x54 */ -} __attribute__((packed)); +} __packed; check_member(apb_dma, channel_swid1, 0x54); /* @@ -164,7 +165,7 @@ struct apb_dma_channel_regs { u32 apb_seq; /* 0x1c */ u32 wcount; /* 0x20 */ u32 word_transfer; /* 0x24 */ -} __attribute__((packed)); +} __packed; check_member(apb_dma_channel_regs, word_transfer, 0x24); struct apb_dma_channel { diff --git a/src/soc/nvidia/tegra124/include/soc/emc.h b/src/soc/nvidia/tegra124/include/soc/emc.h index bae0068e4c..f1ff7f320d 100644 --- a/src/soc/nvidia/tegra124/include/soc/emc.h +++ b/src/soc/nvidia/tegra124/include/soc/emc.h @@ -17,6 +17,7 @@ #include #include +#include enum { EMC_PIN_RESET_MASK = 1 << 8, @@ -313,7 +314,7 @@ struct tegra_emc_regs { uint32_t puterm_width; /* 0x56c */ uint32_t bgbias_ctl0; /* 0x570 */ uint32_t puterm_adj; /* 0x574 */ -} __attribute__((packed)); +} __packed; check_member(tegra_emc_regs, puterm_adj, 0x574); diff --git a/src/soc/nvidia/tegra124/include/soc/spi.h b/src/soc/nvidia/tegra124/include/soc/spi.h index a9ea4eadf9..c56b302339 100644 --- a/src/soc/nvidia/tegra124/include/soc/spi.h +++ b/src/soc/nvidia/tegra124/include/soc/spi.h @@ -17,6 +17,7 @@ #include #include #include +#include struct tegra_spi_regs { u32 command1; /* 0x000: SPI_COMMAND1 */ @@ -34,7 +35,7 @@ struct tegra_spi_regs { u32 rsvd2[31]; /* 0x10c-0x187 reserved */ u32 rx_fifo; /* 0x188: SPI_FIFO2 */ u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */ -} __attribute__((packed)); +} __packed; check_member(tegra_spi_regs, spare_ctl, 0x18c); enum spi_xfer_mode { diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 2737b282e0..74d337caeb 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -13,6 +13,7 @@ */ #include +#include /* Function unit addresses. */ enum { @@ -642,7 +643,7 @@ struct lp0_header { uint32_t destination; // Where to load the blob in iRAM. uint32_t entry_point; // Entry point for the blob. uint32_t code_length; // Length of just the data. -} __attribute__((packed)); +} __packed; struct lp0_header header __attribute__((section(".header"))) = { diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index 1d4934b0a3..76ea4261a0 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include /* for __console definition */ @@ -38,7 +39,7 @@ struct tegra124_uart { uint32_t mcr; // Modem control register. uint32_t lsr; // Line status register. uint32_t msr; // Modem status register. -} __attribute__ ((packed)); +} __packed; static void tegra124_uart_tx_flush(struct tegra124_uart *uart_ptr); static int tegra124_uart_tst_byte(struct tegra124_uart *uart_ptr); diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h index 9c62e6115c..65fb8fe7c9 100644 --- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h @@ -15,9 +15,10 @@ #define _TEGRA210_CLK_RST_H_ #include #include +#include /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ -struct __attribute__ ((__packed__)) clk_rst_ctlr { +struct __packed clk_rst_ctlr { u32 rst_src; /* _RST_SOURCE, 0x000 */ u32 rst_dev_l; /* _RST_DEVICES_L, 0x004 */ u32 rst_dev_h; /* _RST_DEVICES_H, 0x008 */ diff --git a/src/soc/nvidia/tegra210/include/soc/clst_clk.h b/src/soc/nvidia/tegra210/include/soc/clst_clk.h index 89690f8b55..1524a9e900 100644 --- a/src/soc/nvidia/tegra210/include/soc/clst_clk.h +++ b/src/soc/nvidia/tegra210/include/soc/clst_clk.h @@ -14,8 +14,10 @@ #ifndef _TEGRA210_CLST_CLK_H_ #define _TEGRA210_CLST_CLK_H_ +#include + /* Cluster Clock (CLUSTER_CLOCKS_PUBLIC_) regs */ -struct __attribute__ ((__packed__)) clst_clk_ctlr { +struct __packed clst_clk_ctlr { u32 pllx_base; /* _PLLX_BASE, 0x000 */ u32 pllx_misc; /* _PLLX_MISC, 0x004 */ u32 pllx_misc1; /* _PLLX_MISC_1, 0x008 */ diff --git a/src/soc/nvidia/tegra210/include/soc/dma.h b/src/soc/nvidia/tegra210/include/soc/dma.h index 66db52a331..a4a9213a84 100644 --- a/src/soc/nvidia/tegra210/include/soc/dma.h +++ b/src/soc/nvidia/tegra210/include/soc/dma.h @@ -16,6 +16,7 @@ #define __NVIDIA_TEGRA210_DMA_H__ #include +#include #include /* @@ -65,7 +66,7 @@ struct apb_dma { u32 chan_wt_reg2; /* 0x4c */ u32 chan_wr_reg3; /* 0x50 */ u32 channel_swid1; /* 0x54 */ -} __attribute__((packed)); +} __packed; check_member(apb_dma, channel_swid1, 0x54); /* Security enable for DMA channel */ @@ -166,7 +167,7 @@ struct apb_dma_channel_regs { u32 apb_seq; /* 0x1c */ u32 wcount; /* 0x20 */ u32 word_transfer; /* 0x24 */ -} __attribute__((packed)); +} __packed; check_member(apb_dma_channel_regs, word_transfer, 0x24); struct apb_dma_channel { diff --git a/src/soc/nvidia/tegra210/include/soc/emc.h b/src/soc/nvidia/tegra210/include/soc/emc.h index 09bc7c64f0..9e52b6969e 100644 --- a/src/soc/nvidia/tegra210/include/soc/emc.h +++ b/src/soc/nvidia/tegra210/include/soc/emc.h @@ -17,6 +17,7 @@ #include #include +#include enum { EMC_PIN_RESET_MASK = 1 << 8, @@ -465,7 +466,7 @@ struct tegra_emc_regs { uint32_t pmacro_ib_rxrt; /* 0xCF4 */ uint32_t pmacro_training_ctrl0; /* 0xCF8 */ uint32_t pmacro_training_ctrl1; /* 0xCFC */ -} __attribute__((packed)); +} __packed; check_member(tegra_emc_regs, pmacro_training_ctrl1, 0xCFC); diff --git a/src/soc/nvidia/tegra210/include/soc/spi.h b/src/soc/nvidia/tegra210/include/soc/spi.h index 49f786855f..188fa665db 100644 --- a/src/soc/nvidia/tegra210/include/soc/spi.h +++ b/src/soc/nvidia/tegra210/include/soc/spi.h @@ -15,6 +15,7 @@ #ifndef __NVIDIA_TEGRA210_SPI_H__ #define __NVIDIA_TEGRA210_SPI_H__ +#include #include #include #include @@ -35,7 +36,7 @@ struct tegra_spi_regs { u32 rsvd2[31]; /* 0x10c-0x187 reserved */ u32 rx_fifo; /* 0x188: SPI_FIFO2 */ u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */ -} __attribute__((packed)); +} __packed; check_member(tegra_spi_regs, spare_ctl, 0x18c); enum spi_xfer_mode { diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index d3ac67b00f..a6d9533ffa 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -13,6 +13,7 @@ */ #include +#include /* Function unit addresses. */ enum { @@ -1118,7 +1119,7 @@ struct lp0_header { uint32_t destination; // Where to load the blob in iRAM. uint32_t entry_point; // Entry point for the blob. uint32_t code_length; // Length of just the data. -} __attribute__((packed)); +} __packed; struct lp0_header header __attribute__((section(".header"))) = { diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index 1f16067049..608b443dea 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -19,6 +19,7 @@ #include #include #include +#include struct tegra210_uart { union { @@ -38,7 +39,7 @@ struct tegra210_uart { uint32_t mcr; // Modem control register. uint32_t lsr; // Line status register. uint32_t msr; // Modem status register. -} __attribute__ ((packed)); +} __packed; static struct tegra210_uart * const uart_ptr = -- cgit v1.2.3