From 55009af42c39f413c49503670ce9bc2858974962 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Dec 2019 22:03:27 -0800 Subject: Change all clrsetbits_leXX() to clrsetbitsXX() This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/qualcomm/sdm845/clock.c | 14 +++++++------- src/soc/qualcomm/sdm845/usb.c | 16 ++++++++-------- 2 files changed, 15 insertions(+), 15 deletions(-) (limited to 'src/soc/qualcomm/sdm845') diff --git a/src/soc/qualcomm/sdm845/clock.c b/src/soc/qualcomm/sdm845/clock.c index e55495b86e..f3b34cf68a 100644 --- a/src/soc/qualcomm/sdm845/clock.c +++ b/src/soc/qualcomm/sdm845/clock.c @@ -66,7 +66,7 @@ struct clock_config qspi_core_cfg[] = { static int clock_configure_gpll0(void) { /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */ - setbits_le32(&gcc->gpll0.user_ctl, + setbits32(&gcc->gpll0.user_ctl, 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT); @@ -76,7 +76,7 @@ static int clock_configure_gpll0(void) static int clock_configure_mnd(struct sdm845_clock *clk, uint32_t m, uint32_t n, uint32_t d_2) { - setbits_le32(&clk->rcg.cfg, + setbits32(&clk->rcg.cfg, RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); write32(&clk->m, m & CLK_CTL_RCG_MND_BMSK); @@ -110,7 +110,7 @@ static int clock_configure(struct sdm845_clock *clk, clk_cfg[idx].d_2); /* Commit config to RCG*/ - setbits_le32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + setbits32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); return 0; } @@ -125,7 +125,7 @@ static int clock_enable_vote(void *cbcr_addr, void *vote_addr, { /* Set clock vote bit */ - setbits_le32(vote_addr, BIT(vote_bit)); + setbits32(vote_addr, BIT(vote_bit)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)) @@ -138,7 +138,7 @@ static int clock_enable(void *cbcr_addr) { /* Set clock enable bit */ - setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)) @@ -169,9 +169,9 @@ int clock_reset_bcr(void *bcr_addr, bool reset) struct sdm845_bcr *bcr = bcr_addr; if (reset) - setbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + setbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); else - clrbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + clrbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); return 0; } diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c index 8e2b9119ae..56da28e44d 100644 --- a/src/soc/qualcomm/sdm845/usb.c +++ b/src/soc/qualcomm/sdm845/usb.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ -#include #include #include #include +#include #include #include #include @@ -725,7 +725,7 @@ static void qusb2_phy_set_tune_param(struct usb_dwc3_cfg *dwc3) * tune parameters. */ if (tune_val) - clrsetbits_le32(&dwc3->qusb_phy_dig->tune1, + clrsetbits32(&dwc3->qusb_phy_dig->tune1, PORT_TUNE1_MASK, tune_val << 4); } @@ -762,7 +762,7 @@ static void tune_phy(struct usb_dwc3_cfg *dwc3, struct usb_qusb_phy_dig *phy) static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) { /* PWR_CTRL: set the power down bit to disable the PHY */ - setbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + setbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); write32(&dwc3->qusb_phy_pll->analog_controls_two, QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); @@ -782,7 +782,7 @@ static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) tune_phy(dwc3, dwc3->qusb_phy_dig); /* PWR_CTRL1: Clear the power down bit to enable the PHY */ - clrbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + clrbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); write32(&dwc3->qusb_phy_dig->debug_ctrl2, DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); @@ -848,7 +848,7 @@ static void ss_qmp_phy_init(struct usb_dwc3_cfg *dwc3) static void setup_dwc3(struct usb_dwc3 *dwc3) { /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ - clrsetbits_le32(&dwc3->usb3pipectl, + clrsetbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_DELAYP1TRANS, DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); @@ -858,18 +858,18 @@ static void setup_dwc3(struct usb_dwc3 *dwc3) * 2. Set USBTRDTIM to the corresponding value * according to the UTMI+ PHY interface. */ - clrsetbits_le32(&dwc3->usb2phycfg, + clrsetbits32(&dwc3->usb2phycfg, (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | DWC3_GUSB2PHYCFG_PHYIF_MASK), (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | DWC3_GCTL_DISSCRAMBLE), DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); /* configure controller in Host mode */ - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); printk(BIOS_SPEW, "Configure USB in Host mode\n"); } -- cgit v1.2.3