From 62b4de13c656d5a773d78a35192d560c2216d669 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Fri, 12 Dec 2014 17:54:27 -0800 Subject: ipq8064: enable timestamp collection One kilobyte of SRAM needs to be allocated and the feature enabled. BRANCH=storm BUG=chrome-os-partner:34161 TEST=timer error messages do not show up in the coreboot log any more Change-Id: I1d5e5521bf9ae495d4f4f50ff017c846a8420719 Signed-off-by: Patrick Georgi Original-Commit-Id: ffb9bfb0cdfab1391f8ae07669a2ab6b24d88dd7 Original-Change-Id: I60066672334db36f5e7adbef6794d7afd177d292 Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/235893 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/10847 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/qualcomm/ipq806x/Kconfig | 1 + src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'src/soc/qualcomm') diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index ecc52e20f2..9a1e4f99d9 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -7,6 +7,7 @@ config SOC_QC_IPQ806X select ARCH_RAMSTAGE_ARMV7 select BOOTBLOCK_CONSOLE select CHROMEOS_VBNV_FLASH + select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index 426d35b844..cf417bac31 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -34,8 +34,9 @@ SECTIONS OVERLAP_VERSTAGE_ROMSTAGE(0x2A012000, 64K) VBOOT2_WORK(0x2A022000, 16K) PRERAM_CBMEM_CONSOLE(0x2A026000, 32K) + TIMESTAMP(0x2A02E000, 1K) -/* 0x2e400..0x3F000 67KB free */ +/* 0x2e400..0x3F000 67 KB free */ /* Keep the below area reserved at all times, it is used by various QCA components as shared data -- cgit v1.2.3