From 503d12191d11858ec59a0cceb585e8e675c9e907 Mon Sep 17 00:00:00 2001 From: "jinkun.hong" Date: Thu, 31 Jul 2014 14:50:49 +0800 Subject: rk3288: add clock module Call rkclk_init() in bootblock stage. apll = 816MHz, gpll = 594MHz, cpll = 384MHz, dpll = 300MHz arm clk = 816MHz, DDR clk = 300MHz, mpclk = 204MHz, m0clk = 408MHz l2ramclk = 408MHz, atclk = 204MHz, pclk_dbg = 204MHz aclk = 148.5MHz, hclk = 148.5MHz, pclk = 74.25MHz BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: Id5967712e25df5be3a90f5d9ebe8671034deff68 Signed-off-by: Patrick Georgi Original-Commit-Id: d35d9fe7b5925291e9303e5eb21d20dbbdee99d9 Original-Change-Id: I97d953258039f6caa499cef4462be8f1a05ce2ab Original-Signed-off-by: jinkun.hong Original-Reviewed-on: https://chromium-review.googlesource.com/209428 Original-Reviewed-by: Julius Werner Original-Reviewed-by: David Hendricks Original-Commit-Queue: David Hendricks Original-Tested-by: David Hendricks Reviewed-on: http://review.coreboot.org/8858 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/soc/rockchip/rk3288/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/rockchip/rk3288/Makefile.inc') diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 50a1bbfcf6..13c811475b 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -25,15 +25,18 @@ bootblock-y += media.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif +bootblock-y += clock.c romstage-y += cbmem.c romstage-y += timer.c romstage-y += monotonic_timer.c romstage-y += media.c romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += clock.c ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += monotonic_timer.c +ramstage-y += clock.c ramstage-y += media.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c -- cgit v1.2.3