From 4ecccff72f1876c264303aac48cb7143fe36cecc Mon Sep 17 00:00:00 2001 From: Lin Huang Date: Wed, 18 Jan 2017 09:44:34 +0800 Subject: rockchip/rk3399: set edp pclk to 25MHz It may cause an edp aux transfer error if the edp pclk is set too high, so reduce it to 25MHz. BUG=chrome-os-partner:60130 BRANCH=None TEST=Build and Boot Change-Id: Id1063baa5a82637b03c0f1f754181df074ab17cc Signed-off-by: Patrick Georgi Original-Commit-Id: 8f7ce31a7483e765ae0c86f8e62ef51413ee1596 Original-Change-Id: Ibb86c12c1d7c00dc3b4cc7a6bdf3bd6e895cd9f3 Original-Signed-off-by: Lin Huang Original-Reviewed-on: https://chromium-review.googlesource.com/429410 Original-Commit-Ready: Julius Werner Original-Tested-by: Julius Werner Original-Reviewed-by: Julius Werner Reviewed-on: https://review.coreboot.org/18178 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Martin Roth --- src/soc/rockchip/rk3399/include/soc/clock.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/rockchip/rk3399/include') diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 82bf215389..3047f738b0 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -119,5 +119,6 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz); void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); int rkclk_was_watchdog_reset(void); uint32_t rkclk_i2c_clock_for_bus(unsigned bus); +void rkclk_configure_edp(unsigned int hz); #endif /* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */ -- cgit v1.2.3