From e3d78b82a76c6069a8111b278d4af57e9788ef9e Mon Sep 17 00:00:00 2001 From: Lin Huang Date: Tue, 28 Jun 2016 11:10:54 +0800 Subject: rockchip/rk3399: calculate clocks based on parent clock speed Currently aclkm pclkdbg atclk clocks use apll_l as a parent, but the apll_l frequency may change in firmware, so we need to caculate the div value based on the apll_l frequency. BRANCH=None BUG=chrome-os-partner:54376 TEST=Boot from Gru Change-Id: I2bd8886168453ce98efec58b5490c2430762769b Signed-off-by: Martin Roth Original-Commit-Id: 116ae863a504630e2aff056564836d84198fcae2 Original-Change-Id: I7e3a5d9e3f608ddf15592d893117c92767fcd015 Original-Signed-off-by: Lin Huang Original-Signed-off-by: Douglas Anderson Original-Reviewed-on: https://chromium-review.googlesource.com/356397 Original-Reviewed-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/15581 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/rockchip/rk3399/include/soc/clock.h | 1 - 1 file changed, 1 deletion(-) (limited to 'src/soc/rockchip/rk3399/include') diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 806e1ce348..6781b5c691 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -73,7 +73,6 @@ static struct rk3399_pmucru_reg * const pmucru_ptr = (void *)PMUCRU_BASE; static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE; #define OSC_HZ (24*MHz) -#define APLL_HZ (600*MHz) #define GPLL_HZ (594*MHz) #define CPLL_HZ (384*MHz) #define PPLL_HZ (594*MHz) -- cgit v1.2.3