From b4d3d09ded8bbb72007bd4429d32b9b2c6d715a9 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Wed, 13 Jul 2016 23:12:27 -0700 Subject: gru: implement hw reset function Asserting this GPIO will send a signal to the EC to trigger a reset for the AP and the CR50. BRANCH=none BUG=chrome-os-partner:55252 TEST=the device now reboots when it needs to switch between different boot modes instead of hanging with "failed to reboot" message. Change-Id: I8d168e313b6983c96c80f7ad6d70bb84c1ec1d9c Signed-off-by: Martin Roth Original-Commit-Id: 83a4c8ff68ab24a103f2166e948eb23624ea97f7 Original-Change-Id: Idfd20977cf3682bd8933f89e8eec53005e55864e Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/360238 Original-Reviewed-by: Aaron Durbin Original-Reviewed-by: Julius Werner Reviewed-on: https://review.coreboot.org/15718 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/rockchip/rk3399/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/rockchip') diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 28c633835a..7a5e7a1e7a 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -29,6 +29,8 @@ bootblock-y += mmu_operations.c bootblock-y += timer.c verstage-y += ../common/cbmem.c +verstage-y += ../common/gpio.c +verstage-y += gpio.c verstage-y += sdram.c verstage-y += ../common/spi.c verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c -- cgit v1.2.3