From 2f37bd65518865688b9234afce0d467508d6f465 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Thu, 19 Feb 2015 14:51:15 -0800 Subject: arm(64): Globally replace writel(v, a) with write32(a, v) This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/samsung/exynos5420/dmc_init_ddr3.c | 200 ++++++++++++++--------------- 1 file changed, 95 insertions(+), 105 deletions(-) (limited to 'src/soc/samsung/exynos5420/dmc_init_ddr3.c') diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index 8186b6dbdf..6972618ac3 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -47,40 +47,40 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) /* Enable BYPASS mode */ setbits_le32(&exynos_clock->bpll_con1, BYPASS_EN); - writel(MUX_BPLL_SEL_FOUTBPLL, &exynos_clock->clk_src_cdrex); + write32(&exynos_clock->clk_src_cdrex, MUX_BPLL_SEL_FOUTBPLL); do { - val = readl(&exynos_clock->clk_mux_stat_cdrex); + val = read32(&exynos_clock->clk_mux_stat_cdrex); val &= BPLL_SEL_MASK; } while (val != FOUTBPLL); clrbits_le32(&exynos_clock->bpll_con1, BYPASS_EN); /* Specify the DDR memory type as DDR3 */ - val = readl(&exynos_phy0_control->phy_con0); + val = read32(&exynos_phy0_control->phy_con0); val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT); - writel(val, &exynos_phy0_control->phy_con0); + write32(&exynos_phy0_control->phy_con0, val); - val = readl(&exynos_phy1_control->phy_con0); + val = read32(&exynos_phy1_control->phy_con0); val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT); - writel(val, &exynos_phy1_control->phy_con0); + write32(&exynos_phy1_control->phy_con0, val); /* Set Read Latency and Burst Length for PHY0 and PHY1 */ val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); - writel(val, &exynos_phy0_control->phy_con42); - writel(val, &exynos_phy1_control->phy_con42); + write32(&exynos_phy0_control->phy_con42, val); + write32(&exynos_phy1_control->phy_con42, val); - val = readl(&exynos_phy0_control->phy_con26); + val = read32(&exynos_phy0_control->phy_con26); val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); - writel(val, &exynos_phy0_control->phy_con26); + write32(&exynos_phy0_control->phy_con26, val); - val = readl(&exynos_phy1_control->phy_con26); + val = read32(&exynos_phy1_control->phy_con26); val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); - writel(val, &exynos_phy1_control->phy_con26); + write32(&exynos_phy1_control->phy_con26, val); /* Set Driver strength for CK, CKE, CS & CA to 0x7 * Set Driver strength for Data Slice 0~3 to 0x6 @@ -89,8 +89,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET); val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) | (0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET); - writel(val, &exynos_phy0_control->phy_con39); - writel(val, &exynos_phy1_control->phy_con39); + write32(&exynos_phy0_control->phy_con39, val); + write32(&exynos_phy1_control->phy_con39, val); /* ZQ Calibration */ if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control)) @@ -100,31 +100,27 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) clrbits_le32(&exynos_phy1_control->phy_con16, ZQ_CLK_DIV_EN); /* DQ Signal */ - val = readl(&exynos_phy0_control->phy_con14); + val = read32(&exynos_phy0_control->phy_con14); val |= mem->phy0_pulld_dqs; - writel(val, &exynos_phy0_control->phy_con14); - val = readl(&exynos_phy1_control->phy_con14); + write32(&exynos_phy0_control->phy_con14, val); + val = read32(&exynos_phy1_control->phy_con14); val |= mem->phy1_pulld_dqs; - writel(val, &exynos_phy1_control->phy_con14); + write32(&exynos_phy1_control->phy_con14, val); val = MEM_TERM_EN | PHY_TERM_EN; - writel(val, &exynos_drex0->phycontrol0); - writel(val, &exynos_drex1->phycontrol0); - - writel(mem->concontrol | - (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), - &exynos_drex0->concontrol); - writel(mem->concontrol | - (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), - &exynos_drex1->concontrol); + write32(&exynos_drex0->phycontrol0, val); + write32(&exynos_drex1->phycontrol0, val); + + write32(&exynos_drex0->concontrol, + mem->concontrol | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); + write32(&exynos_drex1->concontrol, + mem->concontrol | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); do { - val = readl(&exynos_drex0->phystatus); + val = read32(&exynos_drex0->phystatus); } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); do { - val = readl(&exynos_drex1->phystatus); + val = read32(&exynos_drex1->phystatus); } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); clrbits_le32(&exynos_drex0->concontrol, DFI_INIT_START); @@ -134,41 +130,41 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) update_reset_dll(exynos_drex1, mem->mem_type); /* MEMBASECONFIG0 (CS0) */ - writel(mem->membaseconfig0, &exynos_tzasc0->membaseconfig0); - writel(mem->membaseconfig0, &exynos_tzasc1->membaseconfig0); + write32(&exynos_tzasc0->membaseconfig0, mem->membaseconfig0); + write32(&exynos_tzasc1->membaseconfig0, mem->membaseconfig0); /* MEMBASECONFIG1 (CS1) */ if (mem->chips_per_channel == 2) { - writel(mem->membaseconfig1, &exynos_tzasc0->membaseconfig1); - writel(mem->membaseconfig1, &exynos_tzasc1->membaseconfig1); + write32(&exynos_tzasc0->membaseconfig1, mem->membaseconfig1); + write32(&exynos_tzasc1->membaseconfig1, mem->membaseconfig1); } /* Memory Channel Interleaving Size * Exynos5420 Channel interleaving = 128 bytes */ /* MEMCONFIG0/1 */ - writel(mem->memconfig, &exynos_tzasc0->memconfig0); - writel(mem->memconfig, &exynos_tzasc1->memconfig0); - writel(mem->memconfig, &exynos_tzasc0->memconfig1); - writel(mem->memconfig, &exynos_tzasc1->memconfig1); + write32(&exynos_tzasc0->memconfig0, mem->memconfig); + write32(&exynos_tzasc1->memconfig0, mem->memconfig); + write32(&exynos_tzasc0->memconfig1, mem->memconfig); + write32(&exynos_tzasc1->memconfig1, mem->memconfig); /* Precharge Configuration */ - writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, - &exynos_drex0->prechconfig0); - writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, - &exynos_drex1->prechconfig0); + write32(&exynos_drex0->prechconfig0, + mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT); + write32(&exynos_drex1->prechconfig0, + mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT); /* TimingRow, TimingData, TimingPower and Timingref * values as per Memory AC parameters */ - writel(mem->timing_ref, &exynos_drex0->timingref); - writel(mem->timing_ref, &exynos_drex1->timingref); - writel(mem->timing_row, &exynos_drex0->timingrow); - writel(mem->timing_row, &exynos_drex1->timingrow); - writel(mem->timing_data, &exynos_drex0->timingdata); - writel(mem->timing_data, &exynos_drex1->timingdata); - writel(mem->timing_power, &exynos_drex0->timingpower); - writel(mem->timing_power, &exynos_drex1->timingpower); + write32(&exynos_drex0->timingref, mem->timing_ref); + write32(&exynos_drex1->timingref, mem->timing_ref); + write32(&exynos_drex0->timingrow, mem->timing_row); + write32(&exynos_drex1->timingrow, mem->timing_row); + write32(&exynos_drex0->timingdata, mem->timing_data); + write32(&exynos_drex1->timingdata, mem->timing_data); + write32(&exynos_drex0->timingpower, mem->timing_power); + write32(&exynos_drex1->timingpower, mem->timing_power); if (reset) { /* Send NOP, MRS and ZQINIT commands. @@ -189,8 +185,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) * release pad retention and retain the memory content until the * initialization is complete. */ - writel(PAD_RETENTION_DRAM_COREBLK_VAL, - &exynos_power->padret_dram_cblk_opt); + write32(&exynos_power->padret_dram_cblk_opt, + PAD_RETENTION_DRAM_COREBLK_VAL); do { ret = read32(&exynos_power->padret_dram_status); } while (ret != 0x1); @@ -201,57 +197,55 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) */ for (i = 0; i < 128; i++) { for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(DIRECT_CMD_REFA | - (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex0->directcmd); - writel(DIRECT_CMD_REFA | - (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex1->directcmd); + write32(&exynos_drex0->directcmd, + DIRECT_CMD_REFA | (chip << DIRECT_CMD_CHIP_SHIFT)); + write32(&exynos_drex1->directcmd, + DIRECT_CMD_REFA | (chip << DIRECT_CMD_CHIP_SHIFT)); } } } if (mem->gate_leveling_enable) { - writel(PHY_CON0_RESET_VAL, &exynos_phy0_control->phy_con0); - writel(PHY_CON0_RESET_VAL, &exynos_phy1_control->phy_con0); + write32(&exynos_phy0_control->phy_con0, PHY_CON0_RESET_VAL); + write32(&exynos_phy1_control->phy_con0, PHY_CON0_RESET_VAL); setbits_le32(&exynos_phy0_control->phy_con0, P0_CMD_EN); setbits_le32(&exynos_phy1_control->phy_con0, P0_CMD_EN); val = PHY_CON2_RESET_VAL; val |= INIT_DESKEW_EN; - writel(val, &exynos_phy0_control->phy_con2); - writel(val, &exynos_phy1_control->phy_con2); + write32(&exynos_phy0_control->phy_con2, val); + write32(&exynos_phy1_control->phy_con2, val); - val = readl(&exynos_phy0_control->phy_con1); + val = read32(&exynos_phy0_control->phy_con1); val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); - writel(val, &exynos_phy0_control->phy_con1); + write32(&exynos_phy0_control->phy_con1, val); - val = readl(&exynos_phy1_control->phy_con1); + val = read32(&exynos_phy1_control->phy_con1); val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); - writel(val, &exynos_phy1_control->phy_con1); + write32(&exynos_phy1_control->phy_con1, val); - nLockR = readl(&exynos_phy0_control->phy_con13); + nLockR = read32(&exynos_phy0_control->phy_con13); nLockW_phy0 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2; - nLockR = readl(&exynos_phy0_control->phy_con12); + nLockR = read32(&exynos_phy0_control->phy_con12); nLockR &= ~CTRL_DLL_ON; nLockR |= nLockW_phy0; - writel(nLockR, &exynos_phy0_control->phy_con12); + write32(&exynos_phy0_control->phy_con12, nLockR); - nLockR = readl(&exynos_phy1_control->phy_con13); + nLockR = read32(&exynos_phy1_control->phy_con13); nLockW_phy1 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2; - nLockR = readl(&exynos_phy1_control->phy_con12); + nLockR = read32(&exynos_phy1_control->phy_con12); nLockR &= ~CTRL_DLL_ON; nLockR |= nLockW_phy1; - writel(nLockR, &exynos_phy1_control->phy_con12); + write32(&exynos_phy1_control->phy_con12, nLockR); val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4; for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex0->directcmd); - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex1->directcmd); + write32(&exynos_drex0->directcmd, + val | (chip << DIRECT_CMD_CHIP_SHIFT)); + write32(&exynos_drex1->directcmd, + val | (chip << DIRECT_CMD_CHIP_SHIFT)); } setbits_le32(&exynos_phy0_control->phy_con2, RDLVL_GATE_EN); @@ -260,17 +254,17 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) setbits_le32(&exynos_phy0_control->phy_con0, CTRL_SHGATE); setbits_le32(&exynos_phy1_control->phy_con0, CTRL_SHGATE); - val = readl(&exynos_phy0_control->phy_con1); + val = read32(&exynos_phy0_control->phy_con1); val &= ~(CTRL_GATEDURADJ_MASK); - writel(val, &exynos_phy0_control->phy_con1); + write32(&exynos_phy0_control->phy_con1, val); - val = readl(&exynos_phy1_control->phy_con1); + val = read32(&exynos_phy1_control->phy_con1); val &= ~(CTRL_GATEDURADJ_MASK); - writel(val, &exynos_phy1_control->phy_con1); + write32(&exynos_phy1_control->phy_con1, val); - writel(CTRL_RDLVL_GATE_ENABLE, &exynos_drex0->rdlvl_config); + write32(&exynos_drex0->rdlvl_config, CTRL_RDLVL_GATE_ENABLE); i = TIMEOUT; - while (((readl(&exynos_drex0->phystatus) & RDLVL_COMPLETE_CHO) + while (((read32(&exynos_drex0->phystatus) & RDLVL_COMPLETE_CHO) != RDLVL_COMPLETE_CHO) && (i > 0)) { /* * TODO(waihong): Comment on how long this take to @@ -281,11 +275,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) } if (!i) return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; - writel(CTRL_RDLVL_GATE_DISABLE, &exynos_drex0->rdlvl_config); + write32(&exynos_drex0->rdlvl_config, CTRL_RDLVL_GATE_DISABLE); - writel(CTRL_RDLVL_GATE_ENABLE, &exynos_drex1->rdlvl_config); + write32(&exynos_drex1->rdlvl_config, CTRL_RDLVL_GATE_ENABLE); i = TIMEOUT; - while (((readl(&exynos_drex1->phystatus) & RDLVL_COMPLETE_CHO) + while (((read32(&exynos_drex1->phystatus) & RDLVL_COMPLETE_CHO) != RDLVL_COMPLETE_CHO) && (i > 0)) { /* * TODO(waihong): Comment on how long this take to @@ -296,23 +290,23 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) } if (!i) return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; - writel(CTRL_RDLVL_GATE_DISABLE, &exynos_drex1->rdlvl_config); + write32(&exynos_drex1->rdlvl_config, CTRL_RDLVL_GATE_DISABLE); - writel(0, &exynos_phy0_control->phy_con14); - writel(0, &exynos_phy1_control->phy_con14); + write32(&exynos_phy0_control->phy_con14, 0); + write32(&exynos_phy1_control->phy_con14, 0); val = (0x3 << DIRECT_CMD_BANK_SHIFT); for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex0->directcmd); - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex1->directcmd); + write32(&exynos_drex0->directcmd, + val | (chip << DIRECT_CMD_CHIP_SHIFT)); + write32(&exynos_drex1->directcmd, + val | (chip << DIRECT_CMD_CHIP_SHIFT)); } /* Common Settings for Leveling */ val = PHY_CON12_RESET_VAL; - writel((val + nLockW_phy0), &exynos_phy0_control->phy_con12); - writel((val + nLockW_phy1), &exynos_phy1_control->phy_con12); + write32(&exynos_phy0_control->phy_con12, (val + nLockW_phy0)); + write32(&exynos_phy1_control->phy_con12, (val + nLockW_phy1)); setbits_le32(&exynos_phy0_control->phy_con2, DLL_DESKEW_EN); setbits_le32(&exynos_phy1_control->phy_con2, DLL_DESKEW_EN); @@ -322,22 +316,18 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) dmc_config_prech(mem, exynos_drex0); dmc_config_prech(mem, exynos_drex1); - writel(mem->memcontrol, &exynos_drex0->memcontrol); - writel(mem->memcontrol, &exynos_drex1->memcontrol); + write32(&exynos_drex0->memcontrol, mem->memcontrol); + write32(&exynos_drex1->memcontrol, mem->memcontrol); /* * Set DMC Concontrol: Enable auto-refresh counter, provide * read data fetch cycles and enable DREX auto set powerdown * for input buffer of I/O in none read memory state. */ - writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| - DMC_CONCONTROL_IO_PD_CON(0x2), - &exynos_drex0->concontrol); - writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| - DMC_CONCONTROL_IO_PD_CON(0x2), - &exynos_drex1->concontrol); + write32(&exynos_drex0->concontrol, + mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | DMC_CONCONTROL_IO_PD_CON(0x2)); + write32(&exynos_drex1->concontrol, + mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | DMC_CONCONTROL_IO_PD_CON(0x2)); /* Enable Clock Gating Control for DMC * this saves around 25 mw dmc power as compared to the power -- cgit v1.2.3