From 7524400242be26610df143b5d1d781f875239c45 Mon Sep 17 00:00:00 2001 From: Philipp Hug Date: Sat, 7 Jul 2018 21:34:31 +0200 Subject: uart/sifive: make divisor configurable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SiFive UART on the HiFive Unleashed uses the tlclk as input clock which runs at coreclk / 2. The input frequency is configured in the board code depending on the current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz) Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42 Signed-off-by: Philipp Hug Reviewed-on: https://review.coreboot.org/27440 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer --- src/soc/sifive/fu540/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/sifive/fu540/Kconfig') diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index c438a10162..457d16bb4e 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -20,7 +20,7 @@ config SOC_SIFIVE_FU540 select ARCH_RAMSTAGE_RISCV select BOOTBLOCK_CONSOLE select DRIVERS_UART_SIFIVE - + select UART_OVERRIDE_REFCLK if SOC_SIFIVE_FU540 config RISCV_ARCH -- cgit v1.2.3