From 5fed693a52ed9746900ce58ec12a2b245f08202e Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Thu, 12 Jul 2018 14:56:05 +0800 Subject: riscv: add support for modifying compiler options MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Each HART of a SoC like fu540 supports a different ISA. In order for the coreboot's code can run on each core, need to modify the compile options. So add this code. Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/27442 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Jonathan Neuschäfer Reviewed-by: Philipp Hug --- src/soc/sifive/fu540/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/soc/sifive') diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index d247c280b5..c438a10162 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -23,4 +23,16 @@ config SOC_SIFIVE_FU540 if SOC_SIFIVE_FU540 +config RISCV_ARCH + string + default "rv64imac" + +config RISCV_ABI + string + default "lp64" + +config RISCV_CODEMODEL + string + default "medany" + endif -- cgit v1.2.3