From 2e38dbe5f1a9db76cdf529679faee63fcb6a9c34 Mon Sep 17 00:00:00 2001
From: Xiang Wang <wxjstz@126.com>
Date: Tue, 28 Aug 2018 16:34:29 +0800
Subject: riscv: update mtime initialization
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Add a interface, which is implemented by SoC.

Change-Id: I5524732f6eb3841e43afd176644119b03b5e5e27
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
---
 src/soc/ucb/riscv/Makefile.inc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/soc/ucb/riscv/Makefile.inc')

diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc
index 1072a2b32e..16225c0968 100644
--- a/src/soc/ucb/riscv/Makefile.inc
+++ b/src/soc/ucb/riscv/Makefile.inc
@@ -1,5 +1,6 @@
 ifeq ($(CONFIG_SOC_UCB_RISCV),y)
 
+bootblock-y += mtime.c
 romstage-y += cbmem.c
 ramstage-y += cbmem.c
 
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