From 06766c1efaf7e9f502dc0705f31af0f234824cb7 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 4 Sep 2017 16:13:08 -0600 Subject: amd/stoneyridge: Remove PSP BAR init from cpu init Remove the step of setting PSP BAR3 from cpu_dev_ops .init. The BAR is configured in romstage by AmdInitPost(). Change-Id: I7e77fad3abdcb6482f1b9d849e5922a426dff5f5 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/21492 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/amd/stoneyridge/model_15_init.c | 18 ------------------ 1 file changed, 18 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c index a46f322d14..631e89cb98 100644 --- a/src/soc/amd/stoneyridge/model_15_init.c +++ b/src/soc/amd/stoneyridge/model_15_init.c @@ -30,23 +30,6 @@ #include #include -#include -#include - -void PSPProgBar3Msr(void *Buffer); - -void PSPProgBar3Msr(void *Buffer) -{ - u32 Bar3Addr; - u64 Tmp64; - /* Get Bar3 Addr */ - Bar3Addr = PspLibPciReadPspConfig(0x20); - Tmp64 = Bar3Addr; - printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64); - LibAmdMsrWrite(PSP_MSR_PRIVATE_BLOCK_BAR, &Tmp64, NULL); - LibAmdMsrRead(PSP_MSR_PRIVATE_BLOCK_BAR, &Tmp64, NULL); -} - static void model_15_init(device_t dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); @@ -106,7 +89,6 @@ static void model_15_init(device_t dev) } printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif - PSPProgBar3Msr(NULL); /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); -- cgit v1.2.3