From 3432e556f548c0e61c714b880ce04bf1f3f687bd Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Mon, 20 Jul 2015 17:24:44 -0700 Subject: soc/common/intel: Reset is not dependend upon FSP Remove dependency of common reset code on FSP BRANCH=none BUG=None TEST=Build and run on Braswell and Skylake Original-Change-Id: I00052f29326f691b6d56d2349f99815cafff5848 Original-Signed-off-by: Lee Leahy Original-Reviewed-on: https://chromium-review.googlesource.com/286932 Original-Commit-Queue: Leroy P Leahy Original-Tested-by: Leroy P Leahy Original-Reviewed-by: Aaron Durbin Change-Id: I7f59f0aad7dfae92df28cf20fff2d5a684795d22 Signed-off-by: Lee Leahy Reviewed-on: http://review.coreboot.org/11165 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy --- src/soc/intel/common/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'src/soc') diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 68d3f5ea6c..dfbc6bb729 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -66,7 +66,6 @@ config SOC_INTEL_COMMON_FSP_ROMSTAGE config SOC_INTEL_COMMON_RESET bool default n - depends on PLATFORM_USES_FSP1_1 config SOC_INTEL_COMMON_STACK bool -- cgit v1.2.3