From 3d9462a07f0250cf628b7874620f9f682b7a020e Mon Sep 17 00:00:00 2001 From: Shamile Khan Date: Wed, 21 Mar 2018 14:43:42 -0700 Subject: soc/intel/apollolake: Bypass FSP's deassertion of PERST# signal. BUG=b:76058338 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I1858c7843d16b6b63fc30762a889916bbb9b781a Signed-off-by: Shamile Khan Reviewed-on: https://review.coreboot.org/25311 Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/romstage.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1db2982214..a8a0dd1d44 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -304,6 +304,17 @@ static void soc_memory_init_params(FSPM_UPD *mupd) die("Can not find SoC devicetree\n"); m_cfg->PrmrrSize = config->PrmrrSize; + + /* FSP performs a PERST# signal deassertion for PCIe ports with + * the GPIO address specified in these UPDs. Over-ride the default + * addresses with 0 to bypass PERST# signal deassertion in FSP. + */ + m_cfg->RootPort0Perst = 0; + m_cfg->RootPort1Perst = 0; + m_cfg->RootPort2Perst = 0; + m_cfg->RootPort3Perst = 0; + m_cfg->RootPort4Perst = 0; + m_cfg->RootPort5Perst = 0; #endif } -- cgit v1.2.3