From 3eb8dbaee2eac62438b6c5391c09979bcaed32b0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 13 Jul 2020 01:41:00 +0200 Subject: src: Drop useless cache flush settings in FADT They are ignored if the ACPI_FADT_WBINVD flag is set, which is required on current ACPI versions and only maintained for ACPI 1.0 compatibility. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/soc/amd/picasso/acpi.c | 2 -- src/soc/amd/stoneyridge/acpi.c | 2 -- src/soc/intel/baytrail/fadt.c | 2 -- src/soc/intel/braswell/fadt.c | 2 -- src/soc/intel/broadwell/fadt.c | 2 -- src/soc/intel/common/block/acpi/acpi.c | 2 -- src/soc/intel/denverton_ns/acpi.c | 2 -- src/soc/intel/skylake/fadt.c | 2 -- src/soc/intel/xeon_sp/cpx/acpi.c | 2 -- src/soc/intel/xeon_sp/skx/acpi.c | 2 -- 10 files changed, 20 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index d3966607e2..6d5d937ccb 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -110,8 +110,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ fadt->day_alrm = 0; /* 0x7d these have to be */ diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index fb8a469d34..7f199ccacb 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -82,8 +82,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ fadt->day_alrm = 0; /* 0x7d these have to be */ diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c index b19d4ce6ee..900805b683 100644 --- a/src/soc/intel/baytrail/fadt.c +++ b/src/soc/intel/baytrail/fadt.c @@ -32,8 +32,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; fadt->duty_offset = 1; fadt->duty_width = 0; fadt->day_alrm = 0xd; diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index b19d4ce6ee..900805b683 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -32,8 +32,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; fadt->duty_offset = 1; fadt->duty_width = 0; fadt->day_alrm = 0xd; diff --git a/src/soc/intel/broadwell/fadt.c b/src/soc/intel/broadwell/fadt.c index 4e4074ff6d..2a4019db94 100644 --- a/src/soc/intel/broadwell/fadt.c +++ b/src/soc/intel/broadwell/fadt.c @@ -31,8 +31,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->gpe0_blk_len = 32; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; fadt->duty_offset = 1; fadt->duty_width = 0; fadt->day_alrm = 0xd; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 1ce34fa7f4..9f99984aab 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -114,8 +114,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) /* GPE0 STS/EN pairs each 32 bits wide. */ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->flush_size = 0x400; /* twice of cache size */ - fadt->flush_stride = 0x10; /* Cache line width */ fadt->duty_offset = 1; fadt->day_alrm = 0xd; diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 99782b7ff0..f4204da5ef 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -129,8 +129,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ fadt->duty_offset = 1; fadt->duty_width = 0; diff --git a/src/soc/intel/skylake/fadt.c b/src/soc/intel/skylake/fadt.c index 732f6b6bf5..0c0ae8db7a 100644 --- a/src/soc/intel/skylake/fadt.c +++ b/src/soc/intel/skylake/fadt.c @@ -35,8 +35,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; fadt->duty_offset = 1; fadt->duty_width = 0; fadt->day_alrm = 0xd; diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index db233cbca5..1ca3fc6de6 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -293,8 +293,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) /* GPE0 STS/EN pairs each 32 bits wide. */ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->flush_size = 0x400; /* twice of cache size */ - fadt->flush_stride = 0x10; /* Cache line width */ fadt->duty_offset = 1; fadt->day_alrm = 0xd; diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 13bddfc3bb..478b8a4174 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -252,8 +252,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ fadt->duty_offset = 1; fadt->duty_width = 0; -- cgit v1.2.3