From 5a73fc35e23b15b0a80e2a26553953764907be1d Mon Sep 17 00:00:00 2001
From: Marshall Dawson <marshall.dawson@amd.corp-partner.google.com>
Date: Fri, 24 Jan 2020 09:42:57 -0700
Subject: soc/amd/picasso: Add common PSP support

Add a new psp.c file so the base address can be determined, and select
the common/block/psp feature.

BUG=b:153677737

Change-Id: I322fd11a867a817375ff38a008219f9236c4f2ea
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/2020368
Tested-by: Eric Peers <epeers@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40296
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/picasso/Kconfig      |  1 +
 src/soc/amd/picasso/Makefile.inc |  3 +++
 src/soc/amd/picasso/psp.c        | 22 ++++++++++++++++++++++
 3 files changed, 26 insertions(+)
 create mode 100644 src/soc/amd/picasso/psp.c

(limited to 'src/soc')

diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index d9211b4fb6..842ba0cd37 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_HDA
 	select SOC_AMD_COMMON_BLOCK_SATA
 	select SOC_AMD_COMMON_BLOCK_SMBUS
+	select SOC_AMD_COMMON_BLOCK_PSP_GEN2
 	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select PARALLEL_MP
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index 2f4f00bc04..b79f6274b3 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -44,6 +44,7 @@ romstage-y += tsc_freq.c
 romstage-y += southbridge.c
 romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
 romstage-y += soc_util.c
+romstage-y += psp.c
 
 verstage-y += gpio.c
 verstage-y += i2c.c
@@ -76,6 +77,7 @@ ramstage-y += usb.c
 ramstage-y += tsc_freq.c
 ramstage-y += finalize.c
 ramstage-y += soc_util.c
+ramstage-y += psp.c
 
 all-y += reset.c
 
@@ -84,6 +86,7 @@ smm-y += smi_util.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_DEBUG_SMI) += uart.c
 smm-y += gpio.c
+smm-y += psp.c
 
 CPPFLAGS_common += -I$(src)/soc/amd/picasso
 CPPFLAGS_common += -I$(src)/soc/amd/picasso/include
diff --git a/src/soc/amd/picasso/psp.c b/src/soc/amd/picasso/psp.c
new file mode 100644
index 0000000000..d6eb7d31a3
--- /dev/null
+++ b/src/soc/amd/picasso/psp.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <amdblocks/psp.h>
+
+#define PSP_MAILBOX_OFFSET		0x10570
+#define MSR_CU_CBBCFG			0xc00110a2
+
+void *soc_get_mbox_address(void)
+{
+	uintptr_t psp_mmio;
+
+	psp_mmio = rdmsr(MSR_CU_CBBCFG).lo;
+	if (psp_mmio == 0xffffffff) {
+		printk(BIOS_WARNING, "PSP: MSR_CU_CBBCFG uninitialized\n");
+		return 0;
+	}
+
+	return (void *)(psp_mmio + PSP_MAILBOX_OFFSET);
+}
-- 
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