From 654cc2fe109ea1be4d22447b3d0e6eb22a75b550 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 27 May 2018 13:52:28 +0200 Subject: {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/26574 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Werner Zeh --- src/soc/intel/fsp_baytrail/bootblock/bootblock.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c index 2b1eb10fd7..6f0049f9d0 100644 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c @@ -70,8 +70,7 @@ static void enable_rom_caching(void) msr_t msr; disable_cache(); - set_var_mtrr(1, 0xffffffff - CACHE_ROM_SIZE + 1, - CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); + set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); enable_cache(); /* Enable Variable MTRRs */ -- cgit v1.2.3