From 74ea48efb30f6f72a7a46b352170455c0a33391d Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 29 Jan 2018 12:00:47 -0800 Subject: soc/intel/skylake: Add devicetree variable for PCIe HotPlug Add a variable to fill out the FSP UPD variable for PCIe HotPlug, which allows a mainboard to enable HotPlug on individual root ports. BUG=b:72417777 TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in linux that it is identified as a HotPlug capable root port. Change-Id: I6b1f525e41909a3f81984806c4ef20239032c8d6 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/23511 Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/chip.c | 2 ++ src/soc/intel/skylake/chip.h | 3 +++ src/soc/intel/skylake/chip_fsp20.c | 2 ++ 3 files changed, 7 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 8002270ed9..f60c08d97c 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -121,6 +121,8 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, sizeof(params->PcieRpClkReqNumber)); + memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, + sizeof(params->PcieRpHotPlug)); params->EnableLan = config->EnableLan; params->Cio2Enable = config->Cio2Enable; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 003c44fc91..b77f6dc771 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -231,6 +231,9 @@ struct soc_intel_skylake_config { */ u8 PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + /* Enable/Disable HotPlug support for Root Port */ + u8 PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; + /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index aad918a1ad..3bc66b2501 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -170,6 +170,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->PcieRpAdvancedErrorReporting)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(params->PcieRpLtrEnable)); + memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, + sizeof(params->PcieRpHotPlug)); /* * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for -- cgit v1.2.3