From 8ac6a19155b2e65dec83032e9b6ce9aa9a9e121b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Thu, 20 Sep 2018 16:55:33 +0200 Subject: soc/sifive/fu540: Document #if ENV_ROMSTAGE line MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Idcd72c558e46637b1b99e9613963436fedd4a8b9 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/28699 Reviewed-by: Philipp Hug Reviewed-by: Ronald G. Minnich Tested-by: build bot (Jenkins) --- src/soc/sifive/fu540/clock.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/soc') diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index eb7a8b5483..20dce23a64 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -121,8 +121,8 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI; // 33.33 Mhz after reset #define FU540_BASE_FQY 33330 +/* Clock initialization should only be done in romstage. */ #if ENV_ROMSTAGE - static void init_coreclk(void) { // switch coreclk to input reference frequency before modifying PLL @@ -240,8 +240,7 @@ void clock_init(void) for (int i = 0; i < 256; i++) asm volatile ("nop"); } - -#endif +#endif /* ENV_ROMSTAGE */ int clock_get_coreclk_khz(void) { -- cgit v1.2.3