From 8d9b878f639fdd55d9151e117863fa3a4cbe7ab0 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 29 Jun 2020 17:56:02 -0600 Subject: soc/amd/common/lpc: Skip SERIRQ setup when using eSPI BUG=b:157984427 TEST=check value of PMx054 Signed-off-by: Marshall Dawson Change-Id: I2ca14c137ed784a1a7cfeed969719f46fc8230f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42896 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/common/block/lpc/lpc.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 5e18aad0bb..deadfa2a77 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -25,6 +25,18 @@ /* Most systems should have already enabled the bridge */ void __weak soc_late_lpc_bridge_enable(void) { } +static void setup_serirq(void) +{ + u8 byte; + + /* Set up SERIRQ, enable continuous mode */ + byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE); + if (!CONFIG(SERIRQ_CONTINUOUS_MODE)) + byte |= PM_SERIRQ_MODE; + + pm_write8(PM_SERIRQ_CONF, byte); +} + static void lpc_init(struct device *dev) { u8 byte; @@ -81,12 +93,8 @@ static void lpc_init(struct device *dev) /* Initialize i8254 timers */ setup_i8254(); - /* Set up SERIRQ, enable continuous mode */ - byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE); - if (!CONFIG(SERIRQ_CONTINUOUS_MODE)) - byte |= PM_SERIRQ_MODE; - - pm_write8(PM_SERIRQ_CONF, byte); + if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) + setup_serirq(); } static void lpc_read_resources(struct device *dev) -- cgit v1.2.3