From a7a57701d6297e1d103d13b48fa98e51148670a3 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 4 Aug 2015 10:58:32 -0500 Subject: skylake: do not overlap resources FSP was setting up the TCO registers to be mapped at 0x400. However, the SMBus initialization in romstage was mapping its I/O BAR to 0x400 as well. The result seemed to cause the TCO register to be hidden. However, the board was rebooting in depthcharge when the SMBus device was enabled from a TCO timeout. As the TCO timer was halted before the double resource assignment it's not clear how the TCO was getting re-enabled. In either case, the current behavior is wrong. BUG=chrome-os-partner:42407 BRANCH=None TEST=Built and booted glados w/ SMBus enabled. Original-Change-Id: I43c0d67a76abac51ccfd5105245792981fbcd04c Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/290363 Original-Reviewed-by: Duncan Laurie Change-Id: I3839290768c27626c3fd2d67d5de94c291c1386e Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11180 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/skylake/include/soc/iomap.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 764e9665e2..c56b8e4835 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -21,6 +21,9 @@ #ifndef _SOC_IOMAP_H_ #define _SOC_IOMAP_H_ +/* + * Memory-mapped I/O registers. + */ #define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS #define MCFG_BASE_SIZE 0x4000000 @@ -54,13 +57,20 @@ #define PCH_PWRM_BASE_ADDRESS 0xfe000000 #define PCH_PWRM_BASE_SIZE 0x10000 +/* + * I/O port address space + */ +#define SMBUS_BASE_ADDRESS 0x0efa0 +#define SMBUS_BASE_SIZE 0x20 + #define ACPI_BASE_ADDRESS 0x1800 #define ACPI_BASE_SIZE 0x100 +/* FIXME: not applicable as there is no I/O space for gpio access. */ #define GPIO_BASE_ADDRESS 0x1400 #define GPIO_BASE_SIZE 0x400 -#define SMBUS_BASE_ADDRESS 0x0400 -#define SMBUS_BASE_SIZE 0x10 +#define TCO_BASE_ADDDRESS 0x400 +#define TCO_BASE_SIZE 0x20 #endif -- cgit v1.2.3