From aa6d38859768486d3353edd7aef092b6318ac1bf Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 11 Jan 2019 09:18:20 +0100 Subject: soc/intel/fsp_broadwell_de: Move early_mainboard_romstage_entry() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move early_mainboard_romstage_entry before console_init. Allows to setup a SuperIO, if any, for serial console. Change-Id: I370263a6197a4c0c805352f07fedddbee1b8e247 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/30828 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 003ae2270c..8ddca26be5 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -68,14 +68,16 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_EN, 0x340f); } - console_init(); - init_rtc(); - setup_gpio_io_address(); /* Call into mainboard. */ post_code(0x41); early_mainboard_romstage_entry(); + post_code(0x42); + console_init(); + init_rtc(); + setup_gpio_io_address(); + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB -- cgit v1.2.3