From aaced4a932dc68268cebace63df079673960c17b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 28 Nov 2018 13:53:15 +0100 Subject: cpu/intel/common: Use a common acpi/cpu.asl file Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: David Guckian --- src/soc/intel/apollolake/acpi/cpu.asl | 35 ------------------------------- src/soc/intel/baytrail/acpi/cpu.asl | 36 -------------------------------- src/soc/intel/braswell/acpi/cpu.asl | 36 -------------------------------- src/soc/intel/broadwell/acpi/cpu.asl | 35 ------------------------------- src/soc/intel/cannonlake/acpi/cpu.asl | 35 ------------------------------- src/soc/intel/denverton_ns/acpi/cpu.asl | 37 --------------------------------- src/soc/intel/fsp_baytrail/acpi/cpu.asl | 36 -------------------------------- src/soc/intel/icelake/acpi/cpu.asl | 35 ------------------------------- src/soc/intel/skylake/acpi/cpu.asl | 35 ------------------------------- 9 files changed, 320 deletions(-) delete mode 100644 src/soc/intel/apollolake/acpi/cpu.asl delete mode 100644 src/soc/intel/baytrail/acpi/cpu.asl delete mode 100644 src/soc/intel/braswell/acpi/cpu.asl delete mode 100644 src/soc/intel/broadwell/acpi/cpu.asl delete mode 100644 src/soc/intel/cannonlake/acpi/cpu.asl delete mode 100644 src/soc/intel/denverton_ns/acpi/cpu.asl delete mode 100644 src/soc/intel/fsp_baytrail/acpi/cpu.asl delete mode 100644 src/soc/intel/icelake/acpi/cpu.asl delete mode 100644 src/soc/intel/skylake/acpi/cpu.asl (limited to 'src/soc') diff --git a/src/soc/intel/apollolake/acpi/cpu.asl b/src/soc/intel/apollolake/acpi/cpu.asl deleted file mode 100644 index d42d1bbe51..0000000000 --- a/src/soc/intel/apollolake/acpi/cpu.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit */ -Method (PPCN) -{ - \_PR.CNOT (0x80) -} - -/* Notify OS to re-read Throttle Limit tables */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} diff --git a/src/soc/intel/baytrail/acpi/cpu.asl b/src/soc/intel/baytrail/acpi/cpu.asl deleted file mode 100644 index 5c153f4a59..0000000000 --- a/src/soc/intel/baytrail/acpi/cpu.asl +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit */ -Method (PPCN) -{ - \_PR.CNOT (0x80) -} - -/* Notify OS to re-read Throttle Limit tables */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} diff --git a/src/soc/intel/braswell/acpi/cpu.asl b/src/soc/intel/braswell/acpi/cpu.asl deleted file mode 100644 index 5c153f4a59..0000000000 --- a/src/soc/intel/braswell/acpi/cpu.asl +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit */ -Method (PPCN) -{ - \_PR.CNOT (0x80) -} - -/* Notify OS to re-read Throttle Limit tables */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} diff --git a/src/soc/intel/broadwell/acpi/cpu.asl b/src/soc/intel/broadwell/acpi/cpu.asl deleted file mode 100644 index d42d1bbe51..0000000000 --- a/src/soc/intel/broadwell/acpi/cpu.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit */ -Method (PPCN) -{ - \_PR.CNOT (0x80) -} - -/* Notify OS to re-read Throttle Limit tables */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} diff --git a/src/soc/intel/cannonlake/acpi/cpu.asl b/src/soc/intel/cannonlake/acpi/cpu.asl deleted file mode 100644 index 5f65bd8b4b..0000000000 --- a/src/soc/intel/cannonlake/acpi/cpu.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit */ -Method (PPCN) -{ - \_PR.CNOT (0x80) -} - -/* Notify OS to re-read Throttle Limit tables */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} diff --git a/src/soc/intel/denverton_ns/acpi/cpu.asl b/src/soc/intel/denverton_ns/acpi/cpu.asl deleted file mode 100644 index 673df943ff..0000000000 --- a/src/soc/intel/denverton_ns/acpi/cpu.asl +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 - 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit */ -Method (PPCN) -{ - \_PR.CNOT (0x80) -} - -/* Notify OS to re-read Throttle Limit tables */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} diff --git a/src/soc/intel/fsp_baytrail/acpi/cpu.asl b/src/soc/intel/fsp_baytrail/acpi/cpu.asl deleted file mode 100644 index 5c153f4a59..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/cpu.asl +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit */ -Method (PPCN) -{ - \_PR.CNOT (0x80) -} - -/* Notify OS to re-read Throttle Limit tables */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} diff --git a/src/soc/intel/icelake/acpi/cpu.asl b/src/soc/intel/icelake/acpi/cpu.asl deleted file mode 100644 index 2981c19754..0000000000 --- a/src/soc/intel/icelake/acpi/cpu.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit */ -Method (PPCN) -{ - \_PR.CNOT (0x80) -} - -/* Notify OS to re-read Throttle Limit tables */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} diff --git a/src/soc/intel/skylake/acpi/cpu.asl b/src/soc/intel/skylake/acpi/cpu.asl deleted file mode 100644 index d42d1bbe51..0000000000 --- a/src/soc/intel/skylake/acpi/cpu.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit */ -Method (PPCN) -{ - \_PR.CNOT (0x80) -} - -/* Notify OS to re-read Throttle Limit tables */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} -- cgit v1.2.3