From b17f3d3d3cdd215edcff492699c744a4c85908d0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 24 Oct 2019 00:19:45 +0200 Subject: soc,mb/intel: clean up remaining FSP2.0 socs/boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove CONFIG_...FSP2.0 based if-switches from FSP2.0-only socs/boards Change-Id: Iae92dc2e2328b14c78ac686aaf326bd68430933b Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36279 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Makefile.inc | 2 +- src/soc/intel/cannonlake/Makefile.inc | 2 +- src/soc/intel/icelake/Makefile.inc | 2 +- src/soc/intel/quark/Kconfig | 6 +- src/soc/intel/quark/Makefile.inc | 8 +- src/soc/intel/quark/fsp2_0.c | 25 ----- src/soc/intel/quark/fsp_params.c | 25 +++++ src/soc/intel/quark/romstage/Makefile.inc | 4 +- src/soc/intel/quark/romstage/fsp2_0.c | 160 ------------------------------ src/soc/intel/quark/romstage/fsp_params.c | 160 ++++++++++++++++++++++++++++++ 10 files changed, 195 insertions(+), 199 deletions(-) delete mode 100644 src/soc/intel/quark/fsp2_0.c create mode 100644 src/soc/intel/quark/fsp_params.c delete mode 100644 src/soc/intel/quark/romstage/fsp2_0.c create mode 100644 src/soc/intel/quark/romstage/fsp_params.c (limited to 'src/soc') diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 41faf7243b..5530e5c5ab 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -22,7 +22,7 @@ bootblock-y += uart.c romstage-y += car.c romstage-y += ../../../cpu/intel/car/romstage.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c +romstage-y += romstage.c romstage-y += gspi.c romstage-y += heci.c romstage-y += i2c.c diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 724e141d39..5bc9409521 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -49,7 +49,7 @@ ramstage-y += nhlt.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c -ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 15f7030ba0..80dcdc118c 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -48,7 +48,7 @@ ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c -ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 4ed0377a7b..b752784d15 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -29,6 +29,7 @@ config CPU_SPECIFIC_OPTIONS select C_ENVIRONMENT_BOOTBLOCK select NO_MMCONF_SUPPORT select REG_SCRIPT + select PLATFORM_USES_FSP2_0 select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select SOC_SETS_MSRS @@ -113,8 +114,7 @@ config ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY select ENABLE_DEBUG_LED help Indicate that bootblock_c_entry was entered. If the SD LED does not - light then debug the code between ESRAM and bootblock_c_entry. For - FSP 1.1, use ENABLE_DEBUG_LED_FINDFSP to split this code. + light then debug the code between ESRAM and bootblock_c_entry. config ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY bool "SD LED indicates bootblock_soc_early_init successfully entered" @@ -192,12 +192,10 @@ config FSP_ESRAM_LOC config FSP_M_FILE string - depends on PLATFORM_USES_FSP2_0 default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP_M.fd" config FSP_S_FILE string - depends on PLATFORM_USES_FSP2_0 default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP_S.fd" ##### diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index f1382f5efa..cff089149d 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -37,9 +37,9 @@ romstage-y += reg_access.c romstage-$(CONFIG_STORAGE_TEST) += storage_test.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +romstage-y += reset.c -postcar-y += fsp2_0.c +postcar-y += fsp_params.c postcar-y += i2c.c postcar-y += memmap.c postcar-y += reg_access.c @@ -49,14 +49,14 @@ postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c -ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c +ramstage-y += fsp_params.c ramstage-y += gpio_i2c.c ramstage-y += i2c.c ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += northcluster.c ramstage-y += reg_access.c -ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += reset.c ramstage-y += sd.c ramstage-y += spi.c ramstage-y += spi_debug.c diff --git a/src/soc/intel/quark/fsp2_0.c b/src/soc/intel/quark/fsp2_0.c deleted file mode 100644 index d96d410f9a..0000000000 --- a/src/soc/intel/quark/fsp2_0.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) -{ -} - -asmlinkage void chipset_teardown_car(void) -{ -} diff --git a/src/soc/intel/quark/fsp_params.c b/src/soc/intel/quark/fsp_params.c new file mode 100644 index 0000000000..d96d410f9a --- /dev/null +++ b/src/soc/intel/quark/fsp_params.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) +{ +} + +asmlinkage void chipset_teardown_car(void) +{ +} diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 13963d4b23..d90a3af5d4 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -14,10 +14,8 @@ # romstage-y += car.c -ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-$(CONFIG_DISPLAY_UPD_DATA) += debug.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c -endif # CONFIG_PLATFORM_USES_FSP2_0 +romstage-y += fsp_params.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c deleted file mode 100644 index cd654d74de..0000000000 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016-2017 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "../chip.h" -#include -#include -#include -#include -#include -#include -#include -#include - -void mainboard_romstage_entry(void) -{ - bool s3wake; - - post_code(0x20); - console_init(); - - if (CONFIG(STORAGE_TEST)) { - uint32_t bar; - pci_devfn_t dev; - uint32_t previous_bar; - uint16_t previous_command; - - /* Enable the SD/MMC controller and run the test. Restore - * the BAR and command registers upon completion. - */ - dev = PCI_DEV(0, SD_MMC_DEV, SD_MMC_FUNC); - bar = storage_test_init(dev, &previous_bar, &previous_command); - storage_test(bar, 1); - storage_test_complete(dev, previous_bar, previous_command); - } - - /* Initialize DRAM */ - s3wake = fill_power_state() == ACPI_S3; - fsp_memory_init(s3wake); - - /* Disable the ROM shadow 0x000e0000 - 0x000fffff */ - disable_rom_shadow(); - - /* Initialize the PCIe bridges */ - pcie_init(); -} - -static struct chipset_power_state power_state; - -struct chipset_power_state *get_power_state(void) -{ - return &power_state; -} - -int fill_power_state(void) -{ - power_state.prev_sleep_state = 0; - printk(BIOS_SPEW, "prev_sleep_state %d\n", - power_state.prev_sleep_state); - return power_state.prev_sleep_state; -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) -{ - FSPM_ARCH_UPD *aupd; - const struct soc_intel_quark_config *config; - void *rmu_data; - size_t rmu_data_len; - FSP_M_CONFIG *upd; - - /* Clear SMI and wake events */ - clear_smi_and_wake_events(); - - /* Locate the RMU data file in flash */ - rmu_data = locate_rmu_file(&rmu_data_len); - if (!rmu_data) - die_with_post_code(POST_INVALID_CBFS, - "Microcode file (rmu.bin) not found."); - - /* Locate the configuration data from devicetree.cb */ - config = config_of_soc(); - - /* Update the architectural UPD values. */ - aupd = &fspm_upd->FspmArchUpd; - aupd->BootLoaderTolumSize = cbmem_overhead_size(); - aupd->StackBase = (void *)(CONFIG_FSP_ESRAM_LOC - aupd->StackSize); - aupd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; - - /* Display the ESRAM layout */ - if (CONFIG(DISPLAY_ESRAM_LAYOUT)) { - printk(BIOS_SPEW, "\nESRAM Layout:\n\n"); - printk(BIOS_SPEW, - "+-------------------+ 0x80080000 - ESRAM end\n"); - printk(BIOS_SPEW, "| FSP binary |\n"); - printk(BIOS_SPEW, - "+-------------------+ 0x%08x (CONFIG_FSP_ESRAM_LOC)\n", - CONFIG_FSP_ESRAM_LOC); - printk(BIOS_SPEW, "| FSP stack |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", - aupd->StackBase); - printk(BIOS_SPEW, "| |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", - _car_unallocated_start); - printk(BIOS_SPEW, "| coreboot data |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", - _car_stack_end); - printk(BIOS_SPEW, "| coreboot stack |\n"); - printk(BIOS_SPEW, - "+-------------------+ 0x80000000 - ESRAM start\n\n"); - } - - /* Update the UPD data for MemoryInit */ - upd = &fspm_upd->FspmConfig; - upd->AddrMode = config->AddrMode; - upd->ChanMask = config->ChanMask; - upd->ChanWidth = config->ChanWidth; - upd->DramDensity = config->DramDensity; - upd->DramRonVal = config->DramRonVal; - upd->DramRttNomVal = config->DramRttNomVal; - upd->DramRttWrVal = config->DramRttWrVal; - upd->DramSpeed = config->DramSpeed; - upd->DramType = config->DramType; - upd->DramWidth = config->DramWidth; - upd->EccScrubBlkSize = config->EccScrubBlkSize; - upd->EccScrubInterval = config->EccScrubInterval; - upd->Flags = config->Flags; - upd->FspReservedMemoryLength = config->FspReservedMemoryLength; - upd->RankMask = config->RankMask; - upd->RmuBaseAddress = (uintptr_t)rmu_data; - upd->RmuLength = rmu_data_len; - upd->SerialPortWriteChar = !!console_log_level(BIOS_SPEW) - ? (uintptr_t)fsp_write_line : 0; - upd->SmmTsegSize = CONFIG(HAVE_SMI_HANDLER) ? - config->SmmTsegSize : 0; - upd->SocRdOdtVal = config->SocRdOdtVal; - upd->SocWrRonVal = config->SocWrRonVal; - upd->SocWrSlewRate = config->SocWrSlewRate; - upd->SrInt = config->SrInt; - upd->SrTemp = config->SrTemp; - upd->tCL = config->tCL; - upd->tFAW = config->tFAW; - upd->tRAS = config->tRAS; - upd->tRRD = config->tRRD; - upd->tWTR = config->tWTR; -} diff --git a/src/soc/intel/quark/romstage/fsp_params.c b/src/soc/intel/quark/romstage/fsp_params.c new file mode 100644 index 0000000000..cd654d74de --- /dev/null +++ b/src/soc/intel/quark/romstage/fsp_params.c @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016-2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include "../chip.h" +#include +#include +#include +#include +#include +#include +#include +#include + +void mainboard_romstage_entry(void) +{ + bool s3wake; + + post_code(0x20); + console_init(); + + if (CONFIG(STORAGE_TEST)) { + uint32_t bar; + pci_devfn_t dev; + uint32_t previous_bar; + uint16_t previous_command; + + /* Enable the SD/MMC controller and run the test. Restore + * the BAR and command registers upon completion. + */ + dev = PCI_DEV(0, SD_MMC_DEV, SD_MMC_FUNC); + bar = storage_test_init(dev, &previous_bar, &previous_command); + storage_test(bar, 1); + storage_test_complete(dev, previous_bar, previous_command); + } + + /* Initialize DRAM */ + s3wake = fill_power_state() == ACPI_S3; + fsp_memory_init(s3wake); + + /* Disable the ROM shadow 0x000e0000 - 0x000fffff */ + disable_rom_shadow(); + + /* Initialize the PCIe bridges */ + pcie_init(); +} + +static struct chipset_power_state power_state; + +struct chipset_power_state *get_power_state(void) +{ + return &power_state; +} + +int fill_power_state(void) +{ + power_state.prev_sleep_state = 0; + printk(BIOS_SPEW, "prev_sleep_state %d\n", + power_state.prev_sleep_state); + return power_state.prev_sleep_state; +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) +{ + FSPM_ARCH_UPD *aupd; + const struct soc_intel_quark_config *config; + void *rmu_data; + size_t rmu_data_len; + FSP_M_CONFIG *upd; + + /* Clear SMI and wake events */ + clear_smi_and_wake_events(); + + /* Locate the RMU data file in flash */ + rmu_data = locate_rmu_file(&rmu_data_len); + if (!rmu_data) + die_with_post_code(POST_INVALID_CBFS, + "Microcode file (rmu.bin) not found."); + + /* Locate the configuration data from devicetree.cb */ + config = config_of_soc(); + + /* Update the architectural UPD values. */ + aupd = &fspm_upd->FspmArchUpd; + aupd->BootLoaderTolumSize = cbmem_overhead_size(); + aupd->StackBase = (void *)(CONFIG_FSP_ESRAM_LOC - aupd->StackSize); + aupd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; + + /* Display the ESRAM layout */ + if (CONFIG(DISPLAY_ESRAM_LAYOUT)) { + printk(BIOS_SPEW, "\nESRAM Layout:\n\n"); + printk(BIOS_SPEW, + "+-------------------+ 0x80080000 - ESRAM end\n"); + printk(BIOS_SPEW, "| FSP binary |\n"); + printk(BIOS_SPEW, + "+-------------------+ 0x%08x (CONFIG_FSP_ESRAM_LOC)\n", + CONFIG_FSP_ESRAM_LOC); + printk(BIOS_SPEW, "| FSP stack |\n"); + printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + aupd->StackBase); + printk(BIOS_SPEW, "| |\n"); + printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + _car_unallocated_start); + printk(BIOS_SPEW, "| coreboot data |\n"); + printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + _car_stack_end); + printk(BIOS_SPEW, "| coreboot stack |\n"); + printk(BIOS_SPEW, + "+-------------------+ 0x80000000 - ESRAM start\n\n"); + } + + /* Update the UPD data for MemoryInit */ + upd = &fspm_upd->FspmConfig; + upd->AddrMode = config->AddrMode; + upd->ChanMask = config->ChanMask; + upd->ChanWidth = config->ChanWidth; + upd->DramDensity = config->DramDensity; + upd->DramRonVal = config->DramRonVal; + upd->DramRttNomVal = config->DramRttNomVal; + upd->DramRttWrVal = config->DramRttWrVal; + upd->DramSpeed = config->DramSpeed; + upd->DramType = config->DramType; + upd->DramWidth = config->DramWidth; + upd->EccScrubBlkSize = config->EccScrubBlkSize; + upd->EccScrubInterval = config->EccScrubInterval; + upd->Flags = config->Flags; + upd->FspReservedMemoryLength = config->FspReservedMemoryLength; + upd->RankMask = config->RankMask; + upd->RmuBaseAddress = (uintptr_t)rmu_data; + upd->RmuLength = rmu_data_len; + upd->SerialPortWriteChar = !!console_log_level(BIOS_SPEW) + ? (uintptr_t)fsp_write_line : 0; + upd->SmmTsegSize = CONFIG(HAVE_SMI_HANDLER) ? + config->SmmTsegSize : 0; + upd->SocRdOdtVal = config->SocRdOdtVal; + upd->SocWrRonVal = config->SocWrRonVal; + upd->SocWrSlewRate = config->SocWrSlewRate; + upd->SrInt = config->SrInt; + upd->SrTemp = config->SrTemp; + upd->tCL = config->tCL; + upd->tFAW = config->tFAW; + upd->tRAS = config->tRAS; + upd->tRRD = config->tRRD; + upd->tWTR = config->tWTR; +} -- cgit v1.2.3