From b1e4bd0d28bb65474c0a954374124f21cac05972 Mon Sep 17 00:00:00 2001
From: Kenji Chen <kenji.chen@intel.com>
Date: Mon, 16 Nov 2015 17:08:32 +0800
Subject: Braswell: Separate L1 Sub State init procedure for boards.

Original-Reviewed-on: https://chromium-review.googlesource.com/312743
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>

Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: https://review.coreboot.org/12750
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
---
 src/soc/intel/braswell/Kconfig | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src/soc')

diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index c546e403a5..a64505ec47 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -28,7 +28,6 @@ config CPU_SPECIFIC_OPTIONS
 	select PCIEXP_ASPM
 	select PCIEXP_CLK_PM
 	select PCIEXP_COMMON_CLOCK
-	select PCIEXP_L1_SUB_STATE
 	select PLATFORM_USES_FSP1_1
 	select REG_SCRIPT
 	select SOC_INTEL_COMMON
-- 
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