From c3c55210ee598e2dfcfc0bbe664cd703e6fdf3fe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 17 Jun 2020 10:34:26 +0300 Subject: ACPI: Replace smm_setup_structures() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/amd/picasso/Kconfig | 1 + src/soc/amd/picasso/smi.c | 5 ----- src/soc/amd/stoneyridge/Kconfig | 1 + src/soc/amd/stoneyridge/smi.c | 5 ----- src/soc/intel/baytrail/smm.c | 19 ------------------- src/soc/intel/baytrail/southcluster.c | 2 +- src/soc/intel/braswell/acpi.c | 2 +- src/soc/intel/braswell/smm.c | 19 ------------------- src/soc/intel/broadwell/lpc.c | 2 +- src/soc/intel/broadwell/smi.c | 19 ------------------- src/soc/intel/common/block/acpi/acpi.c | 2 +- src/soc/intel/common/block/smm/smm.c | 19 ------------------- src/soc/intel/denverton_ns/acpi.c | 2 +- src/soc/intel/denverton_ns/smm.c | 16 ---------------- src/soc/intel/skylake/acpi.c | 2 +- src/soc/intel/xeon_sp/Kconfig | 1 + src/soc/intel/xeon_sp/cpx/acpi.c | 2 +- src/soc/intel/xeon_sp/skx/acpi.c | 2 +- 18 files changed, 11 insertions(+), 110 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 2df0b6a120..fd2a2053fb 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS select UDK_2017_BINDING select HAVE_CF9_RESET select SUPPORT_CPU_UCODE_IN_CBFS + select ACPI_NO_SMI_GNVS config MEMLAYOUT_LD_FILE string diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c index ba36e65da6..125dde601c 100644 --- a/src/soc/amd/picasso/smi.c +++ b/src/soc/amd/picasso/smi.c @@ -11,11 +11,6 @@ #include #include -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); -} - /** Set the EOS bit and enable SMI generation from southbridge */ void global_smi_enable(void) { diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 47642a9fda..9bb5604391 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select SSE2 select RTC + select ACPI_NO_SMI_GNVS config AMD_APU_STONEYRIDGE bool diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c index a3473aafc5..fb6d3484ad 100644 --- a/src/soc/amd/stoneyridge/smi.c +++ b/src/soc/amd/stoneyridge/smi.c @@ -10,11 +10,6 @@ #include #include -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); -} - /** Set the EOS bit and enable SMI generation from southbridge */ void global_smi_enable(void) { diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 58238db627..c70388abad 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -97,22 +97,3 @@ void global_smi_enable(void) { smm_southbridge_enable(PWRBTN_EN | GBL_EN); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((uint32_t)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index fb63a567fa..679c04d491 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -494,7 +494,7 @@ static void southcluster_inject_dsdt(const struct device *device) if (gnvs) { acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 53379a0da4..1290d625ac 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -512,7 +512,7 @@ void southcluster_inject_dsdt(const struct device *device) gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index e3ebc32304..3f3c53fa74 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -99,22 +99,3 @@ void global_smi_enable(void) { smm_southbridge_enable(PWRBTN_EN | GBL_EN); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((uint32_t)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index b841291086..1e96286990 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -584,7 +584,7 @@ static void southcluster_inject_dsdt(const struct device *device) if (gnvs) { acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 9d8d25e841..317da0cc2d 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -86,22 +86,3 @@ static void __unused southbridge_clear_smi_status(void) /* Set EOS bit so other SMIs can occur. */ enable_smi(EOS); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((u32)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 8d75c9a147..c497399ba2 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -240,7 +240,7 @@ void southbridge_inject_dsdt(const struct device *device) if (gnvs) { acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index 0b120a7023..2fd97da221 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -70,22 +70,3 @@ void global_smi_enable_no_pwrbtn(void) { smm_southbridge_enable(GBL_EN); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((u32)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 3b3e37a01b..014625caa6 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -292,7 +292,7 @@ void southcluster_inject_dsdt(const struct device *device) if (gnvs) { acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index b4970adf9d..e7ed28d827 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -56,19 +56,3 @@ void global_smi_enable(void) { smm_southbridge_enable(PWRBTN_EN | GBL_EN); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile("outb %%al, %%dx\n\t" - : /* ignore result */ - : "a"(APM_CNT_GNVS_UPDATE), "b"((uint32_t)gnvs), - "d"(APM_CNT)); -} diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 6ff836a932..414a14f4e0 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -655,7 +655,7 @@ void southbridge_inject_dsdt(const struct device *device) if (gnvs) { acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 66833017ae..954256236b 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -38,6 +38,7 @@ config CPU_SPECIFIC_OPTIONS select POSTCAR_STAGE select IOAPIC select PARALLEL_MP + select ACPI_NO_SMI_GNVS select SMP select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index abaa45397e..026185714e 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -120,7 +120,7 @@ void southbridge_inject_dsdt(const struct device *device) if (gnvs) { acpi_create_gnvs(gnvs); /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ - // smm_setup_structures(gnvs, NULL, NULL); + // apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 3da2025e53..17da9a929f 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -968,7 +968,7 @@ void southbridge_inject_dsdt(const struct device *device) if (gnvs) { acpi_create_gnvs(gnvs); /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ - // smm_setup_structures(gnvs, NULL, NULL); + // apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); -- cgit v1.2.3