From ce9f422b512c376ba0eeec41db92d9a87155105a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 25 Jun 2018 18:53:36 +0300 Subject: x86/car: Replace reference of copy_and_run location MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For cases with POSTCAR_STAGE=y this reference pulled in the implementation of run_ramstage() which we would not call. Using _program results with the same region being marked as WRPROT-cacheble. Change-Id: Ie1eaf6f5bb8baa13e946112c4fc3d854dbf750a3 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/27232 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Keith Hui --- src/soc/intel/broadwell/romstage/cache_as_ram.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc') diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index d1bb3eef48..fd9f829286 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -136,7 +136,7 @@ clear_mtrrs: * IMPORTANT: The following calculation _must_ be done at runtime. See * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $copy_and_run, %eax + movl $_program, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr -- cgit v1.2.3