From e206e2e7ff91ec9ebe7789eab37510874de9edf4 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 11 Apr 2021 12:06:26 -0700 Subject: soc/intel/cnl and mainboards: Drop `cnl_configure_pads()` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is done") introduced a workaround in coreboot for `soc/intel/cannonlake` platforms to save and restore GPIO configuration performed by mainboard across call to FSP Silicon Init (FSP-S). This workaround was required because FSP-S was configuring GPIOs differently than mainboard resulting in boot and runtime issues because of misconfigured GPIOs. This issue has since been fixed in FSP (verified with FSP v1263 on hatch). However, there were still 4 boards in coreboot using `cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u and system76/lemp9 were tested to ensure that this workaround is no longer required. This change drops the workaround using `cnl_configure_pads()` and updates all mainboards to use `gpio_configure_pads()` instead. Signed-off-by: Furquan Shaikh Tested-by: Angel Pons (Tested purism/librem_cnl) Tested-by: Michael Niewöhner (Tested clevo/cml-u which is similar to system76/lemp9) Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248 Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/chip.c | 31 ----------------------------- src/soc/intel/cannonlake/include/soc/gpio.h | 2 +- 2 files changed, 1 insertion(+), 32 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 4f467a1ab7..c651c59826 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include @@ -140,33 +139,6 @@ const char *soc_acpi_name(const struct device *dev) } #endif -/* - * TODO(furquan): Get rid of this workaround once FSP is fixed. Currently, FSP-S - * configures GPIOs when it should not and this results in coreboot GPIO - * configuration being overwritten. Until FSP is fixed, maintain the reference - * of GPIO config table from mainboard and use that to re-configure GPIOs after - * FSP-S is done. - */ -void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads) -{ - static const struct pad_config *g_cfg; - static size_t g_num_pads; - - /* - * If cfg and num_pads are passed in from mainboard, maintain a - * reference to the GPIO table. - */ - if ((cfg == NULL) || (num_pads == 0)) { - cfg = g_cfg; - num_pads = g_num_pads; - } else { - g_cfg = cfg; - g_num_pads = num_pads; - } - - gpio_configure_pads(cfg, num_pads); -} - void soc_init_pre_device(void *chip_info) { /* Perform silicon specific init. */ @@ -175,9 +147,6 @@ void soc_init_pre_device(void *chip_info) /* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob(); - /* TODO(furquan): Get rid of this workaround once FSP is fixed. */ - cnl_configure_pads(NULL, 0); - soc_gpio_pm_configuration(); /* swap enabled PCI ports in device tree if needed */ diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h index 9ffa8f1bc2..f204ca2510 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio.h +++ b/src/soc/intel/cannonlake/include/soc/gpio.h @@ -19,7 +19,7 @@ #ifndef __ACPI__ struct pad_config; -void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads); + /* * Routine to perform below operations: * 1. SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register -- cgit v1.2.3