From 2093c4f7c220068e630b756dd19b89ab1ddec88e Mon Sep 17 00:00:00 2001 From: Dave Frodin Date: Fri, 13 Jun 2014 08:12:48 -0600 Subject: AMD/agesa: Add functions for AMD PCI IRQ routing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Port the changes that were made in amd/cimx to amd/agesa as were done in: commit c93a75a5ab067f86104028b74d92fc54cb939cd5 Author: Mike Loptien Date: Fri Jun 6 15:16:29 2014 -0600 AMD/CIMx: Add functions for AMD PCI IRQ routing This change also moves the PCI INT functions to southbridge/amd so that they can be used by CIMX and AGESA. The amd/persimmon board is updated for this change. Signed-off-by: Dave Frodin Change-Id: I525be90f9cf8e825e162d53a7ecd1e69c6e27637 Reviewed-on: http://review.coreboot.org/6065 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- .../amd/agesa/hudson/amd_pci_int_defs.h | 84 ++++++++++++++ .../amd/agesa/hudson/amd_pci_int_types.h | 44 ++++++++ src/southbridge/amd/agesa/hudson/pci.c | 25 +++++ src/southbridge/amd/agesa/hudson/pci_devs.h | 121 +++++++++++++++++++++ 4 files changed, 274 insertions(+) create mode 100644 src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h create mode 100644 src/southbridge/amd/agesa/hudson/amd_pci_int_types.h create mode 100644 src/southbridge/amd/agesa/hudson/pci_devs.h (limited to 'src/southbridge/amd/agesa') diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h new file mode 100644 index 0000000000..01f769c46d --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMD_PCI_INT_DEFS_H +#define AMD_PCI_INT_DEFS_H + +/* + * PIRQ and device routing - these define the index + * into the FCH PCI_INTR 0xC00/0xC01 interrupt + * routing table + */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#define FCH_INT_TABLE_SIZE 0x54 +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#define FCH_INT_TABLE_SIZE 0x42 +#endif + +#define PIRQ_NC 0x1F /* Not Used */ +#define PIRQ_A 0x00 /* INT A */ +#define PIRQ_B 0x01 /* INT B */ +#define PIRQ_C 0x02 /* INT C */ +#define PIRQ_D 0x03 /* INT D */ +#define PIRQ_E 0x04 /* INT E */ +#define PIRQ_F 0x05 /* INT F */ +#define PIRQ_G 0x06 /* INT G */ +#define PIRQ_H 0x07 /* INT H */ +#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ +#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ +#define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ +#define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ +#define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ +#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ +#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ +#define PIRQ_SCI 0x10 /* SCI IRQ */ +#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ +#define PIRQ_ASF 0x12 /* ASF */ +#define PIRQ_HDA 0x13 /* HDA 14h.2 */ +#define PIRQ_FC 0x14 /* FC */ +#define PIRQ_GEC 0x15 /* GEC */ +#define PIRQ_PMON 0x16 /* Performance Monitor */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#define PIRQ_SD 0x17 /* SD */ +#endif +#define PIRQ_IMC0 0x20 /* IMC INT0 */ +#define PIRQ_IMC1 0x21 /* IMC INT1 */ +#define PIRQ_IMC2 0x22 /* IMC INT2 */ +#define PIRQ_IMC3 0x23 /* IMC INT3 */ +#define PIRQ_IMC4 0x24 /* IMC INT4 */ +#define PIRQ_IMC5 0x25 /* IMC INT5 */ +#define PIRQ_OHCI1 0x30 /* USB OHCI 12h.0 */ +#define PIRQ_EHCI1 0x31 /* USB EHCI 12h.2 */ +#define PIRQ_OHCI2 0x32 /* USB OHCI 13h.0 */ +#define PIRQ_EHCI2 0x33 /* USB EHCI 13h.2 */ +#define PIRQ_OHCI3 0x34 /* USB OHCI 16h.0 */ +#define PIRQ_EHCI3 0x35 /* USB EHCI 16h.2 */ +#define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ +#define PIRQ_IDE 0x40 /* IDE 14h.1 */ +#define PIRQ_SATA 0x41 /* SATA 11h.0 */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#define PIRQ_SD 0x42 /* SD 14h.7 */ +#define PIRQ_GPP0 0x50 /* GPP INT 0 */ +#define PIRQ_GPP1 0x51 /* GPP INT 1 */ +#define PIRQ_GPP2 0x52 /* GPP INT 2 */ +#define PIRQ_GPP3 0x53 /* GPP INT 3 */ +#endif + +#endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h new file mode 100644 index 0000000000..75efd67192 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMD_PCI_INT_TYPES_H +#define AMD_PCI_INT_TYPES_H + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +const char * intr_types[] = { + [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", + [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", + [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t", + [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", + [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", + [0x40] = "IDE\t", "SATA\t", + [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" +}; +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +const char * intr_types[] = { + [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", + [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", + [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t", + [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", + [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", + [0x40] = "RSVD\t", "SATA\t", +}; +#endif + +#endif /* AMD_PCI_INT_TYPES_H */ diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 58498f4ab6..e8836e4c7d 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,11 +24,35 @@ #include #include #include "hudson.h" +#include +#include static void pci_init(struct device *dev) { } +/* + * Update the PCI devices with a valid IRQ number + * that is set in the mainboard PCI_IRQ structures. + */ +static void set_pci_irqs(void *unused) +{ + /* Write PCI_INTR regs 0xC00/0xC01 */ + write_pci_int_table(); + + /* Write IRQs for all devicetree enabled devices */ + write_pci_cfg_irqs(); +} + +/* + * Hook this function into the PCI state machine + * on entry into BS_DEV_ENABLE. + */ +BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { + BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, + set_pci_irqs, NULL), +}; + static struct pci_operations lops_pci = { .set_subsystem = 0, }; diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h new file mode 100644 index 0000000000..b66a23258c --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AGESA_HUDSON_PCI_DEVS_H_ +#define _AGESA_HUDSON_PCI_DEVS_H_ + +#define BUS0 0 + +/* XHCI */ +#define XHCI_DEV 0x10 +#define XHCI_FUNC 0 +#define XHCI_DEVID 0x7814 +#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) + +/* SATA */ +#define SATA_DEV 0x11 +#define SATA_FUNC 0 +#define SATA_IDE_DEVID 0x7800 +#define AHCI_DEVID_MS 0x7801 +#define AHCI_DEVID_AMD 0x7804 +#define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC) + +/* OHCI */ +#define OHCI1_DEV 0x12 +#define OHCI1_FUNC 0 +#define OHCI2_DEV 0x13 +#define OHCI2_FUNC 0 +#define OHCI3_DEV 0x16 +#define OHCI3_FUNC 0 +#define OHCI4_DEV 0x14 +#define OHCI4_FUNC 5 +#define OHCI_DEVID 0x7807 +#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC) +#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC) +#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC) +#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC) + +/* EHCI */ +#define EHCI1_DEV 0x12 +#define EHCI1_FUNC 2 +#define EHCI2_DEV 0x13 +#define EHCI2_FUNC 2 +#define EHCI3_DEV 0x22 +#define EHCI3_FUNC 2 +#define EHCI_DEVID 0x7808 +#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC) +#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC) +#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC) + +/* SMBUS */ +#define SMBUS_DEV 0x14 +#define SMBUS_FUNC 0 +#define SMBUS_DEVID 0x780B +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) + +/* IDE */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#define IDE_DEV 0x14 +#define IDE_FUNC 1 +# define IDE_DEVID 0x780C +# define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) +#endif + +/* HD Audio */ +#define HDA_DEV 0x14 +#define HDA_FUNC 2 +#define HDA_DEVID 0x780D +#define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC) + +/* LPC BUS */ +#define PCU_DEV 0x14 +#define LPC_FUNC 3 +#define LPC_DEVID 0x780E +#define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC) + +/* PCI Ports */ +#define SB_PCI_PORT_DEV 0x14 +#define SB_PCI_PORT_FUNC 4 +# define SB_PCI_PORT_DEVID 0x780F +# define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC) + +/* SD Controller */ +#define SD_DEV 0x14 +#define SD_FUNC 7 +#define SD_DEVID 0x7806 +#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) + +/* PCIe Ports */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#define SB_PCIE_DEV 0x15 +#define SB_PCIE_PORT1_FUNC 0 +#define SB_PCIE_PORT2_FUNC 1 +#define SB_PCIE_PORT3_FUNC 2 +#define SB_PCIE_PORT4_FUNC 3 +#define SB_PCIE_PORT1_DEVID 0x7820 +#define SB_PCIE_PORT2_DEVID 0x7821 +#define SB_PCIE_PORT3_DEVID 0x7822 +#define SB_PCIE_PORT4_DEVID 0x7823 +#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) +#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) +#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) +#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) +#endif + +#endif /* _AGESA_HUDSON_PCI_DEVS_H_ */ -- cgit v1.2.3