From dbec2d4090e40d1d8e1fd06e8d4180d3fa685d4d Mon Sep 17 00:00:00 2001 From: Eric Biederman Date: Thu, 21 Oct 2004 10:44:08 +0000 Subject: - Bump the LinuxBIOS major version - Rename chip_config chip_operations throughout the tree - Fix Config.lb on most of the Opteron Ports - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids - Add detection of devices that are on the motherboard (i.e. In Config.lb) - Baby step in getting the resource limit handling correct, Ignore fixed resources - Only call enable_childrens_resources on devices we know will have children For some busses like i2c it is non-sense and we don't want it. - Set the resource limits for pnp devices resources. - Improve the resource size detection for pnp devices. - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels - Added a header file to hold the prototype of isa_dma_init - Fixed most of the superio chips so the should work now, the via superio pci device is the exception. - The code compiles and runs so it is time for me to go to bed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/amd8111/amd8111.c | 58 ++++++++++++++++------------------- 1 file changed, 27 insertions(+), 31 deletions(-) (limited to 'src/southbridge/amd/amd8111/amd8111.c') diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c index a9b132cdaf..6e7022cd77 100644 --- a/src/southbridge/amd/amd8111/amd8111.c +++ b/src/southbridge/amd/amd8111/amd8111.c @@ -9,31 +9,32 @@ void amd8111_enable(device_t dev) device_t lpc_dev; device_t bus_dev; unsigned index; - uint32_t dword; - uint16_t reg_old, reg; - uint8_t byte; - + unsigned reg_old, reg; /* See if we are on the behind the amd8111 pci bridge */ bus_dev = dev->bus->dev; if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) && - (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) { + (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) + { unsigned devfn; devfn = bus_dev->path.u.pci.devfn + (1 << 3); lpc_dev = dev_find_slot(bus_dev->bus->secondary, devfn); index = ((dev->path.u.pci.devfn & ~7) >> 3) + 8; + if (dev->path.u.pci.devfn == 2) { /* EHCI */ + index = 16; + } } else { unsigned devfn; devfn = (dev->path.u.pci.devfn) & ~7; lpc_dev = dev_find_slot(dev->bus->secondary, devfn); index = dev->path.u.pci.devfn & 7; } - - if ((!lpc_dev) || (index >= 16)) { + if ((!lpc_dev) || (index >= 17)) { return; } if ((lpc_dev->vendor != PCI_VENDOR_ID_AMD) || - (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) { + (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) + { uint32_t id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); if (id != (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8111_ISA << 16))) { @@ -41,34 +42,29 @@ void amd8111_enable(device_t dev) } } - /* Now read the vendor and device id */ - dword= pci_read_config32(dev, PCI_VENDOR_ID); -#if 0 - printk_debug(" %s dev->vendor= %04x, dev->device= %04x, id = %08x\n", dev_path(dev), dev->vendor, dev->device, dword); -#endif - - if (dword == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8111_USB2 << 16))) { - if(!dev->enabled) { - byte = pci_read_config8(lpc_dev, 0x47); - byte |= (1<<7); - pci_write_config8(lpc_dev, 0x47, byte); - return; + if (index < 16) { + reg = reg_old = pci_read_config16(lpc_dev, 0x48); + reg &= ~(1 << index); + if (dev->enabled) { + reg |= (1 << index); + } + if (reg != reg_old) { + pci_write_config16(lpc_dev, 0x48, reg); } - - } - - reg = reg_old = pci_read_config16(lpc_dev, 0x48); - reg &= ~(1 << index); - if (dev->enabled) { - reg |= (1 << index); } - if (reg != reg_old) { - pci_write_config16(lpc_dev, 0x48, reg); + else if (index == 16) { + reg = reg_old = pci_read_config8(lpc_dev, 0x47); + reg &= ~(1 << 7); + if (!dev->enabled) { + reg |= (1 << 7); + } + if (reg != reg_old) { + pci_write_config8(lpc_dev, 0x47, reg); + } } - } struct chip_operations southbridge_amd_amd8111_ops = { - .name = "AMD 8111 Southbridge", + .name = "AMD 8111", .enable_dev = amd8111_enable, }; -- cgit v1.2.3