From 9fe4d797a37671a65053add3f7cca27397db0b9b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Sat, 16 Jan 2010 17:53:38 +0000 Subject: coreboot used to have two different "APIs" for memory accesses: read32(unsigned long addr) vs readl(void *addr) and write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr) read32 was only available in __PRE_RAM__ stage, while readl was used in stage2. Some unclean implementations then made readl available to __PRE_RAM__ too which results in really messy includes and code. This patch fixes all code to use the read32/write32 variant, so that we can remove readl/writel in another patch. Signed-off-by: Stefan Reinauer Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/amd8111/amd8111_nic.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/southbridge/amd/amd8111') diff --git a/src/southbridge/amd/amd8111/amd8111_nic.c b/src/southbridge/amd/amd8111/amd8111_nic.c index d326d83dda..98ac62b5d7 100644 --- a/src/southbridge/amd/amd8111/amd8111_nic.c +++ b/src/southbridge/amd/amd8111/amd8111_nic.c @@ -54,12 +54,12 @@ static void nic_init(struct device *dev) /* Hard Reset PHY */ printk_debug("Reseting PHY... "); if (conf->phy_lowreset) { - writel(VAL0 | PHY_RST_POL | RESET_PHY , (void *)(mmio + CMD3)); + write32((void *)(mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); } else { - writel(VAL0 | RESET_PHY, (void *)(mmio + CMD3)); + write32((void *)(mmio + CMD3), VAL0 | RESET_PHY); } mdelay(15); - writel(RESET_PHY, (void *)(mmio + CMD3)); + write32((void *)(mmio + CMD3), RESET_PHY); printk_debug("Done\n"); } -- cgit v1.2.3