From 6209c8299a4bdcdb51cd6bf0c43c571ed575ad96 Mon Sep 17 00:00:00 2001 From: Kerry She Date: Thu, 18 Aug 2011 18:44:00 +0800 Subject: AMD SB800 southbridge update This patch enables access to the registers of the hardware monitor logical device in the superio via isa ports 0x295/0x296. Previously this was not enabled in the SB8xx LPC device. This is required for initialisation in init_hwm() in src/superio/winbond/w83627hf/superio.c and also by OS-level sensor monitoring such as lm-sensors to access temperature, fan monitoring and control and voltage registers. asrock/e350m1 and advansus/a785e-i mainboard changes are included herein. Change-Id: I2176885549277b335c0c41b48457d09b9b76b703 Signed-off-by: Per Hansen Signed-off-by: Kerry She Reviewed-on: http://review.coreboot.org/159 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/southbridge/amd/cimx/sb800/SBPLATFORM.h') diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 89b4dc3c85..164a65156f 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -120,6 +120,7 @@ typedef union _PCI_ADDR { #define cimIrConfigDefault 0x00 // Disable #define cimSpiFastReadEnableDefault 0x01 // Enable #define cimSpiFastReadSpeedDefault 0x01 // 33 MHz +#define cimSioHwmPortEnableDefault FALSE // GPP/AB Controller #define cimNbSbGen2Default TRUE #define cimAlinkPhyPllPowerDownDefault TRUE -- cgit v1.2.3