From 9bcdbf8eaa0c73d130ba555163f89fa1759c8c99 Mon Sep 17 00:00:00 2001
From: zbao <fishbaozi@gmail.com>
Date: Thu, 5 Apr 2012 13:18:49 +0800
Subject: Add Southbridge support for S3.

1. Add some CIMX call for S3.
2. Detect sleep type.

Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/621
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
---
 src/southbridge/amd/cimx/sb800/early.c | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src/southbridge/amd/cimx/sb800/early.c')

diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index 9d49a52d54..f692897dcc 100644
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
@@ -23,9 +23,11 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>		/* inl, outl */
 #include <arch/romcc_io.h>	/* device_t */
+#include <arch/acpi.h>
 #include "SBPLATFORM.h"
 #include "sb_cimx.h"
 #include "cfg.h"		/*sb800_cimx_config*/
+#include "cbmem.h"
 
 
 #if CONFIG_RAMINIT_SYSINFO == 1
@@ -80,3 +82,9 @@ void sb800_clk_output_48Mhz(void)
         *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
 }
 
+#if CONFIG_HAVE_ACPI_RESUME == 1
+int acpi_is_wakeup_early(void)
+{
+	return (acpi_get_sleep_type() == 3);
+}
+#endif
-- 
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