From 5ff7c13e858a31addf1558731a12cf6c753b576d Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 31 Oct 2011 12:56:45 -0700 Subject: remove trailing whitespace Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/amd/cimx/sb900/Amd.h | 0 src/southbridge/amd/cimx/sb900/AmdSbLib.h | 0 src/southbridge/amd/cimx/sb900/SbEarly.h | 0 src/southbridge/amd/cimx/sb900/SbPlatform.h | 0 src/southbridge/amd/cimx/sb900/bootblock.c | 6 +++--- src/southbridge/amd/cimx/sb900/cbtypes.h | 0 src/southbridge/amd/cimx/sb900/chip.h | 0 src/southbridge/amd/cimx/sb900/chip_name.c | 0 src/southbridge/amd/cimx/sb900/early.c | 2 +- src/southbridge/amd/cimx/sb900/late.c | 0 src/southbridge/amd/cimx/sb900/lpc.c | 0 src/southbridge/amd/cimx/sb900/lpc.h | 0 src/southbridge/amd/cimx/sb900/smbus.c | 0 src/southbridge/amd/cimx/sb900/smbus.h | 0 14 files changed, 4 insertions(+), 4 deletions(-) mode change 100755 => 100644 src/southbridge/amd/cimx/sb900/Amd.h mode change 100755 => 100644 src/southbridge/amd/cimx/sb900/AmdSbLib.h mode change 100755 => 100644 src/southbridge/amd/cimx/sb900/SbEarly.h mode change 100755 => 100644 src/southbridge/amd/cimx/sb900/SbPlatform.h mode change 100755 => 100644 src/southbridge/amd/cimx/sb900/bootblock.c mode change 100755 => 100644 src/southbridge/amd/cimx/sb900/cbtypes.h mode change 100755 => 100644 src/southbridge/amd/cimx/sb900/chip.h mode change 100755 => 100644 src/southbridge/amd/cimx/sb900/chip_name.c mode change 100755 => 100644 src/southbridge/amd/cimx/sb900/early.c mode change 100755 => 100644 src/southbridge/amd/cimx/sb900/late.c mode change 100755 => 100644 src/southbridge/amd/cimx/sb900/lpc.c mode change 100755 => 100644 src/southbridge/amd/cimx/sb900/lpc.h mode change 100755 => 100644 src/southbridge/amd/cimx/sb900/smbus.c mode change 100755 => 100644 src/southbridge/amd/cimx/sb900/smbus.h (limited to 'src/southbridge/amd/cimx/sb900') diff --git a/src/southbridge/amd/cimx/sb900/Amd.h b/src/southbridge/amd/cimx/sb900/Amd.h old mode 100755 new mode 100644 diff --git a/src/southbridge/amd/cimx/sb900/AmdSbLib.h b/src/southbridge/amd/cimx/sb900/AmdSbLib.h old mode 100755 new mode 100644 diff --git a/src/southbridge/amd/cimx/sb900/SbEarly.h b/src/southbridge/amd/cimx/sb900/SbEarly.h old mode 100755 new mode 100644 diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h old mode 100755 new mode 100644 diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c old mode 100755 new mode 100644 index e04cec0e04..e84743bc20 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -73,8 +73,8 @@ static void sb900_enable_rom(void) pci_io_write_config32(dev, 0x44, dword); /* SB900 LPC Bridge 0:20:3:48h. - * BIT0: Port Enable for SuperIO 0x2E-0x2F - * BIT1: Port Enable for SuperIO 0x4E-0x4F + * BIT0: Port Enable for SuperIO 0x2E-0x2F + * BIT1: Port Enable for SuperIO 0x4E-0x4F * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) * BIT6: Port Enable for RTC IO 0x70-0x73 * BIT21: Port Enable for Port 0x80 @@ -86,7 +86,7 @@ static void sb900_enable_rom(void) /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */ /* Set the 4MB enable bits */ word = pci_io_read_config16(dev, 0x6c); - word = 0xFFC0; + word = 0xFFC0; pci_io_write_config16(dev, 0x6c, word); } diff --git a/src/southbridge/amd/cimx/sb900/cbtypes.h b/src/southbridge/amd/cimx/sb900/cbtypes.h old mode 100755 new mode 100644 diff --git a/src/southbridge/amd/cimx/sb900/chip.h b/src/southbridge/amd/cimx/sb900/chip.h old mode 100755 new mode 100644 diff --git a/src/southbridge/amd/cimx/sb900/chip_name.c b/src/southbridge/amd/cimx/sb900/chip_name.c old mode 100755 new mode 100644 diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c old mode 100755 new mode 100644 index bd4fd4fa22..1176ca598c --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -142,7 +142,7 @@ void sb_Late_Post(void) //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, // VerifyImage() will fail, LocateImage() take minitues to find the image. sbLatePost(&sb_early_cfg); - + //Set ACPI SCI IRQ to 0x9. data = CONFIG_ACPI_SCI_IRQ; outb(0x10, 0xC00); diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c old mode 100755 new mode 100644 diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c old mode 100755 new mode 100644 diff --git a/src/southbridge/amd/cimx/sb900/lpc.h b/src/southbridge/amd/cimx/sb900/lpc.h old mode 100755 new mode 100644 diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c old mode 100755 new mode 100644 diff --git a/src/southbridge/amd/cimx/sb900/smbus.h b/src/southbridge/amd/cimx/sb900/smbus.h old mode 100755 new mode 100644 -- cgit v1.2.3