From 520717dff196e1d1ed61f72a8abadbc114ee6ba1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Sun, 15 Dec 2019 21:37:48 +0200
Subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK
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Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37440
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/amd/cimx/sb800/Makefile.inc |  2 --
 src/southbridge/amd/cimx/sb800/bootblock.c  | 25 +++----------------------
 2 files changed, 3 insertions(+), 24 deletions(-)

(limited to 'src/southbridge/amd/cimx')

diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc
index 5a68d0732e..2c516485f2 100644
--- a/src/southbridge/amd/cimx/sb800/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb800/Makefile.inc
@@ -16,9 +16,7 @@
 
 # SB800 Platform Files
 
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
 bootblock-y += bootblock.c
-endif
 
 romstage-y += cfg.c
 romstage-y += early.c
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index b4f03dad7e..d42e7eef1d 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -13,7 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
+#include <amdblocks/acpimmio.h>
+#include <arch/bootblock.h>
 #include <device/pci_ops.h>
 
 static void enable_rom(void)
@@ -79,17 +80,6 @@ static void enable_spi_fast_mode(void)
 	pci_io_write_config32(dev, 0xa0, save);
 }
 
-static void enable_acpimmio_decode_pm24(void)
-{
-	u8 reg8;
-
-	outb(0x24, 0xCD6);
-	reg8 = inb(0xCD7);
-	reg8 |= 1;
-	reg8 &= ~(1 << 1);
-	outb(reg8, 0xCD7);
-}
-
 static void enable_clocks(void)
 {
 	u32 reg32;
@@ -109,7 +99,7 @@ static void enable_clocks(void)
 	*acpi_mmio = reg32;
 }
 
-static void bootblock_southbridge_init(void)
+void bootblock_early_southbridge_init(void)
 {
 	/* Setup the ROM access for 2M */
 	enable_rom();
@@ -120,12 +110,3 @@ static void bootblock_southbridge_init(void)
 	enable_acpimmio_decode_pm24();
 	enable_clocks();
 }
-
-#if !CONFIG(ROMCC_BOOTBLOCK)
-#include <bootblock_common.h>
-
-void bootblock_soc_early_init(void)
-{
-	bootblock_southbridge_init();
-}
-#endif
-- 
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